# Two circuits with diferent clock speeds

Discussion in 'General Electronics Chat' started by The Kadet, Apr 27, 2016.

Apr 27, 2016
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Two circuits with diferent clock speeds How to get them to work togueder?

For example in a computer the memory clock speed is diferent from the processor's clock speed, the bus clock speed is diferent from the piriferals bus and so on...

How are these things coordinated?

2. ### eetech00 Active Member

Jun 8, 2013
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They are all derived from the same clock source....the "master clock"

3. ### BR-549 Well-Known Member

Sep 22, 2013
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A computer, the memory for a computer and a processor are an array of switches.

And everything that the computer or processor does, is just a matter of turning the right switch, on or off, at the right time.

A program is a list of switching instructions.

Everything is controlled by switching switches.

Apr 27, 2016
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So the processor clock gives impulses in the from of square wave to the entire sisthem?

How is that possible when the power suply cables are conected to the motherboard and the circuits runing the the processor arent that thick?
And then is not there power dissipation on board?

The memory flip flops work at the same 2+ ghz as the processor!?

5. ### jpanhalt AAC Fanatic!

Jan 18, 2008
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Clocks of different speeds can be synchronized, usually as a simple 2^n multiple. You can also have master-slave relationships for communication wherein the slave follows the master's clock only during the communication. Clock signals do not require heavy cables, since the current supplies is quite small.

John

Apr 27, 2016
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How can it be sincronized just for comunication in the bus? with multiple's is a good idea.

7. ### AnalogKid Distinguished Member

Aug 1, 2013
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Internally, the main processor clock is divided down to run all of the internal sections (instruction decode, cache management, ALU, etc.) in synchronism. It is the two external buses, memory and I/O, that need to be managed. Both are clocked by a frequency derived from the system clock, either by straight division, phase-locked loop, direct digital synthesis.

The external buses do not have to be directly related to the CPU clock. For example, the PCI bus runs at 66 MHz or 133 MHz no matter what the CPU clock is. The processor requests something, then goes away a does something else until the subsystem signals that the result is ready. Or if the processor is writing a string of data, it sends out some bytes or words, then does something else until the subsystem signals that it has digested that data and is ready for more.

Of course, the details vary a lot from one system to another.

ak

Last edited: Apr 27, 2016
8. ### hp1729 Well-Known Member

Nov 23, 2015
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Why is there a need for being synchronized? A system has many different clock sources. No need for synchronism. No concern for power systems.

9. ### dl324 Distinguished Member

Mar 30, 2015
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Huh???

In a computer/microprocessor, all of the clocks need to be synchronized.

10. ### dl324 Distinguished Member

Mar 30, 2015
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All modern microprocessors use PLL's for frequency synthesis.

11. ### hp1729 Well-Known Member

Nov 23, 2015
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Some do. I can see processor and memory being synchronized..Video runs on its own clock speed. Serial I/O runs on its own clock speed. How many crystal oscillators are in your computer? Interrupts and polling take care of the differences.
PLL? Crystals and ceramic resonators.

12. ### Picbuster Member

Dec 2, 2013
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You are all right and wrong its depends on the system designed.
sync- or async sync all hardware functions use the same master async all different clocks running freely and handover information on handshake, polling or interrupt.
Handshake: you may send now or I have data for you. polling: read prog loops and collect, when flag set by sender, the data in senders xmit register clear after successful read. (eq loop circuit runs at 2GB and sender(eq RTC) processor runs at 32Khz from a different source .)
Interrupt: set flag when data is to be collected. ( do not mix up with handshake looks similar but is not)
Each mechanism, or in combination, has it's own unique pro and contra to be selected by the designer to create an optimal usage of the resources.

13. ### hp1729 Well-Known Member

Nov 23, 2015
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Okay, not even memory needs to be synchronous. I agree the design is popular with simple microprocessor but larger systems may not be so. There are / were asynchronous bus systems where the processor starts a memory or I/O cycle but the length of the cycle is up to the memory or I/O device. 68K (Motorola) microprocessor based systems had this carry over from DEC PDP-11 type designs.

14. ### WBahn Moderator

Mar 31, 2012
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Huh? No concern for power systems? Try connecting two megawatt generators together without synchronizing them.

If the clocks aren't properly synchronized, then what happens when you try to sample data with a part of the system running from one clock at the same time that it is being changed by another part of the system running from a different clock. In general ... pandemonium. Some of the bits are from the old data, some are from the new data, and some may be metastable. Clock synchronization prevents this. If you can't synchronize clocks then you have to register them across the clock domain boundaries using a FIFO or FIFO-like approach. This adds complexity, circuitry, delay, and power consumption that can all be avoided if the clock domains can be synchronized.

15. ### hp1729 Well-Known Member

Nov 23, 2015
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Ah, good point there. Yes, it certainly would be important in generators. And yes, FIFOs are a remedy between unsynchronized systems. 74LS670 for instance.