Two bit numbers comparator using one 2 to 4 decoder

Discussion in 'Homework Help' started by cdummie, Feb 12, 2015.

  1. cdummie

    Thread Starter Member

    Feb 6, 2015
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    Basically, problem is, i don't know how to create two bit numbers comparator using one decoder and standard logic gates. I don't even know if it's possible with just one 2 to 4 decoder. Only thing i got so far is the truth table.
    Screenshot_1.png
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    What are X, Y, and Z?

    I can guess, but engineering isn't about guessing.

    Define your inputs and outputs.

    If you can use standard logic gates, then you can do anything because anything (logic-wise) can be done with standard logic gates. If you need more 2-to-4 decoders, make them out of standard logic gates.

    You need to be more specific on what the constraints are on your design.
     
  3. cdummie

    Thread Starter Member

    Feb 6, 2015
    104
    1
    I believe you know, but X is active if A1A0 is greater than B1B0, else if B1B0 is greater than A1A0 Z is active, else Y is active. I am not sure if it's allowed to use more than one 2 to 4 decoder, but anyway i want to know how can i do it with one 2 to 4 decoder, and yes i can use standard logic gates.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    Well, if you were tasked with implementing those truth tables with standard logic gates (no mention of decoders being made), could you do it?

    If so, then you're done.

    You can use a 2 to 4 decode as part of the logic, but it doesn't really add anything if you are allowed unlimited use of standard logic gates in addition.

    You might use the decoder to do some initial parsing of the problem. For instance, what if you but the msb of each value into the decoder. What information does each decoder output tell you without even considering the lsb states?
     
  5. cdummie

    Thread Starter Member

    Feb 6, 2015
    104
    1
    I should do it using decoder 2 to 4 and standard logic gates, i made the truth table and i had the problem with implementing it using decoder. I know how to implement it with standard logic gates. I just minimized X, Y and Z using Karnaugh maps and this is what i got for X:
    Screenshot_1.png
    I believe this is correct, but the problem is that i have to use decoder 2 to 4, what i thought is that i could in this case, for example, use first output of the decoder whose inputs are B1 and B0 as one of the two inputs in AND gate, second input would be A1 but i don't know if i could do that, i mean if it's correct.
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    Let's sanity check your solution to X.

    Each term you have requires A1=1. Does that make sense? Is it really impossible for A>B to be true if A1=0?

    You have A1·B1'·B0' + A1·A0·B0' + A1·B1'

    X is HI if A>B

    The last term takes care of the case A=1? and B=0?

    But doesn't that cover the first term entirely?

    What about A=01 and B=00? Which term covers that?

    Does your schematic even match your equation?
     
  7. cdummie

    Thread Starter Member

    Feb 6, 2015
    104
    1
    Actually i wrote A1 instead of A0 in the first term, it was typing mistake. I think that rest of it should be correct.
     
  8. WBahn

    Moderator

    Mar 31, 2012
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    Okay. So now do the other two. Since you can use all the standard logic gates you want, you can do anything you want with the decoder. Tie its inputs LO and then use AND the output that is HI with one of the one of the other signals (which means that it won't change the other signal). As you've described things, that meets the requirements of the assignment.

    Now, if you want to use the decoder in a meaningful way, consider what I suggested in Post #4.
     
  9. MrAl

    Well-Known Member

    Jun 17, 2014
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    Hello there,

    Just to note, if you can use a simple PROM then you can program the outputs to be whatever you need them to be, comparison just one possibility. For comparing two 2 bit numbers, you'd need four address lines, and since you need 3 outputs you'd need a data path of 4 (because you might not be able to find one with 3). So you could use a 16x4 bit PROM or EEPROM, which would have 4 address lines and 4 outputs lines but you'd only use 3 output lines unless of course you want to extend the functionality.
    The program code is very simple because you just go through all 16 possible combinations of the address lines and force the output bits to be what they need to be for that combination.
    For example, for case 00, 00, you would have a '1' out on say output A, and zeros on all the other outputs B,C, and D. The A output here would be the 'equals' output.
     
  10. WBahn

    Moderator

    Mar 31, 2012
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    He has stated that he is allowed to use one 2-to4 decoder and basic logic gates.
     
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