Hello,

Is there a way to turn off automatic netlist update in LTSpice to speed up my schematic construction? Since I am building a large network, I would rather generate the netlist after I finish building the whole circuit than have the netlist update each time I place components. Thanks!

 

I'm not aware of such an option. About how many components constitute a 'large' network? Unless you're running LTS on an abacus the netlist build time is hardly noticeable with 100 or so components. What can take ages is the simulation itself; but things go much faster if you can simulate a chunk/module at a time if the circuit is complex.

 

I'm not aware of such an option. About how many components constitute a 'large' network? Unless you're running LTS on an abacus the netlist build time is hardly noticeable with 100 or so components. What can take ages is the simulation itself; but things go much faster if you can simulate a chunk/module at a time if the circuit is complex.

I am building a circuit with over 20000 components and counting since we still do not know how large we would like to expand it but thanks a lot for the very helpful suggestion. I think this solution is better.