# TTL XOR Logic Gate Theory of Operation

Discussion in 'General Electronics Chat' started by Electrozapper, Dec 9, 2015.

1. ### Electrozapper Thread Starter New Member

Dec 9, 2015
13
1
I attempted to post earlier but experienced trouble with my schematic. Being a site newbie is erksome at times. Anyway, I have studied from All About Circuits the TTL NOT Gate, the TTL NAND/AND Gates, and the TTL NOR/OR Gates. AAC has wonderful theories of circuit operation when it comes to these circuits. Howbeit, the link below takes you to my circuit in question. It is the 2 input TTL XOR Logic Gate Circuit: (oh, it is the IC 7486, 14 pin package, Exclusive OR Gate, if that data helps).

http://www.interfacebus.com/ic-exclusive-or-gate-dual-input-dip.html

In my earlier attempt to post I tried to copy and paste the circuit here...but that failed. So, hopefully the provided link will be of use.

Now, due to the depth of explanations on the aforementioned AAC topics (that is, TTL NOT, TTL NAND, etc.), I can see that the far left of the circuit is the usual right and left steering diodes. Also, due to the AAC prior lessons, I can discern that the far right of the schematic is the totem pole output section of the circuit (instead of the open collector variety). Howbeit, the in-between stuff has me completely lost. Could someone provide me with the depth of circuit explanation for this TTL XOR Gate as I encountered from the prior topics? Thanks.

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2. ### crutschow Expert

Mar 14, 2008
13,505
3,382
The XOR function means the output is a logic high when either one of the inputs is also high, but the output is a logic low when the inputs are either both high or both low.
This function is generated by the two transistors in the center of the schematic.
Can you figure out how they do that or do you need a more detailed description?

3. ### Electrozapper Thread Starter New Member

Dec 9, 2015
13
1
Thanks for answering. Yes, I shall need a more detailed description. Again, thank you for your help. Electrozapper

4. ### hp1729 Well-Known Member

Nov 23, 2015
2,105
235
Looking at those two transistors, if the circuits feeding then are different one feeds a low to an emitter and the other feeds an enable to the base. The circuit outputs a low. If both circuits give out a low both transistors are off and the output is high. If both outputs are high again both are turned off.

5. ### Electrozapper Thread Starter New Member

Dec 9, 2015
13
1
Thank you. Hmmmmm, let me chew on that awhile. Armed with that information, I shall re-examine the circuit. If I still have questions, I shall re-ask...if that is okay with you? Thanks. Electrozapper

6. ### Electrozapper Thread Starter New Member

Dec 9, 2015
13
1
Okay, after having attempted numerous site searches, I am forced to ask a few more questions.

I have attempted to redraw the schematic with labels...all without success. All right, then, I shall have to attempt explaining my labeling. Assuming you are looking at the schematic, from left to right, top to bottom, the first transistors I shall label Q1 (top) and Q2 (bottom). Okay, that gets the steering diodes out of the way. Sure wished I could label my drawing...it'd be so much easier and much faster. Anywho, the next two BJTs to the right would be labelled Q3 (top) and Q4 (bottom). Moving rightward again, Q5 (top) and Q6 (bottom). Of note, of all of this up to this point, I can fully grasp why it does work. In truth, this entire segment (Q1 to Q6) works like the AAC descriptions from prior lessons (NOT, NAND, etc.). Then, more rightward we go, Q7 (top) and Q8 (bottom). These demons confuse the water out of me. They are not arranged as I am used to seeing bias strategies....one BJT (Q7) even has its base tied to Q8's emiiter???? Huh? Okay, without putting you to sleep, the other transistors I have labeled going rightward, top to bottom, Q9 through Q11...Q10 at top and Q11 at bottom making up the totem pole output. Now, Q9 through Q11 make sense to me based upon prior TTL logic gate studies. But, the Q7 and Q8 have me lost as to how they even function. Q7 has its base connected to Q8's emitter but with Q8's emitter I can find no tie in to the negative rail for proper bias. The other parts of the circuit I can fully trace and understand but it seems Q7 and Q8 are just floating. Can you explain these BJTs (if you have the time) or refer me to a site that I might study them from? Thanks, again. Electrozapper

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7. ### crutschow Expert

Mar 14, 2008
13,505
3,382
Below is the schematic with some parts labeled (didn't check to see if it's the same as you described).

If you understand the Input A and Input B stages then you know that when their input is high, their outputs (at the collectors of Q3 and Q4 respectively are low and vice versa.
The outputs of these two input stages go to Q6 and Q5.

When Input A and B are both low, then the bases and emitters of Q5 and Q6 are all high. This means that no current flows through Q5 and Q6 and the current from R1 goes through the base of Q7 causing an OUTPUT Low.

When Inputs A and B are both high then the bases and emitters of Q5 and Q6 are all low. Again no current flows through Q5 and Q6, and the OUTPUT is still Low.

When only Input A is high, then the base of Q5 is high and its emitter is low. Q5 thus conducts the current from R1 to ground (logic low), turning off Q7, making the OUTPUT High.

Similarly when only Input B is high, the base of Q6 is high and its emitter is low, conducting the current from R1 to ground and again giving an OUTPUT High.

All this gives the XOR function.

Make sense?

Electrozapper and absf like this.
8. ### hp1729 Well-Known Member

Nov 23, 2015
2,105
235

Your Q7 and Q8 ... when the input to the base of Q7 is high (enabled) and the emitter of it is pulled low Q7 is turned on, giving a low out. If the opposite is true Q8 is turned on. So if the inputs to the gate are different we get a low out of Q7 / Q8.
If both of the inputs are low both of the inputs to Q7 and Q8 are high and they are off.
If both of the inputs are high we have a low to both of the bases of Q7 and Q8 and they are both off again.

9. ### Electrozapper Thread Starter New Member

Dec 9, 2015
13
1
YES! Thank You. I really think I now do have it. It does indeed make sense. At times, I was seeking where what was taken to ground but just simply overlooked it. Okay, spot check me on this. By the way, thanks for your patience and your majorly needed help. All right, looking at your labeled schematic, when Input A is Low (0) and Input B is High (1), down the line Q6 and Q4 are fully on (saturated) and draw Q7eb to Ground...making Q7 off and Q9 (bottom transistor of totem pole) is subsequently off (high output...1). This makes sense to me because Q7 being off draws no current for R3 to bias Q9eb on. Then (if I truly am getting this), when the Input A is High (1) and Input B is Low (0), again down the road a bit Q5 and Q3 are fully on (saturated) and once more draw Q7eb to Ground...making Q7 off (again) and making Q9 (bottom transistor of totem pole output) subsequently off for another high output (1). Once more this makes sense to me because, again, Q7 being off draws zero current for R3 to bias Q9eb on. How am I doing? I do believe I got it this time around. Again, thanks so much. Electrozapper