I'm using two decade counters to count up to 12 and then recycle back to 01. The logic I've used for the recycle was a 3 input NAND which takes inputs from bit 1 and 2 from the 1's counter, and bit 1 from the 10's counter (when the number hits 13). The output of the NAND gate is connected to two active low inputs: CLR for the 1's and LOAD for the 10's (for loading 1).

My problem is that only the CLR gets activated, even though the logic level on the two wires is exactly the same.

Here is a diagram of the specific part of my circuit:
http://i.imagehost.org/0406/circuit.png
(The two counters are inverted: the counter on the right is the 10's and the one on the left is the 1's)

Might my circuit using too many gates be a problem? Maybe using some buffer yes gates would help? I'm completely stuck.

 

Found my own problem. The 74160 IC has a synchronous load while the reset is asynchronous. It would reset before the next clockpulse and the NAND gate would no longer be active.