ttl NAND gate

Discussion in 'Homework Help' started by rainaby, Nov 9, 2011.

  1. rainaby

    Thread Starter New Member

    Nov 6, 2011
    9
    0
    how can we assume that Vce(sat) is the operating condition for all the transistors in a ttl nand gate?? it should depend upon the voltages being applied but we ourselves assume it as such while explaning its operation.
     
  2. crutschow

    Expert

    Mar 14, 2008
    12,977
    3,220
    Logic signals are fixed levels of a logic 1 or logic 0. Normally the logic high level is above the minimum required for logic 1 and logic low is below the maximum allowed for logic 0. If the voltages are between those two levels then the gate output level is undefined.
     
Loading...