TTL Logic help needed

Discussion in 'The Projects Forum' started by Phiplex, May 3, 2009.

  1. Phiplex

    Thread Starter New Member

    May 3, 2009
    2
    0
    Need help designing TTL logic for attached timing diagram.
    First edge of Input A signal should always trigger the output high (=1).
    The second (and not the first) edge of Input B signal (during output = 1) should lower the output again (=0). Please help !
     
    Last edited: May 3, 2009
  2. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    657
    This worked when I simulated it.
     
  3. Phiplex

    Thread Starter New Member

    May 3, 2009
    2
    0
    Thank you very very much, Ron. You made my day :D /Phiplex
     
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