TTL Digital Logic Design

Discussion in 'Homework Help' started by samprots, Sep 21, 2009.

  1. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    Alright where do I begin..
    Ok I am trying to drive a bi-directional motor for 10 seconds one direction, then brake for 10 seconds, then run the reverse direction for another 10 seconds, this sequence is started using a push button switch.

    Here are my rules to follow:
    1. When power is turned on motor must not run
    2. When a momentary switch is pressed motor should run for 10 seconds then stop.
    3. The motor must remain stopped for 10 seconds.
    4. After the 10 second pause the motor should spin in the opposite direction.
    5. After 10 seconds the motor should stop again and must wait for the switch to be pressed again.

    Brake is active low and direction is determined by pulling high or low off my two wire control.

    So far I have a working H-bridge and two wire control, those I know are working I am just trying to design the logic behind it to incorporate timing.

    Parts available to me are 555's, J/K FF's, and various logic gates(and, or, not) resistors, caps, etc.

    So far I have set up a "One Shot" and my timing is correct for my output "high 10 seconds" then back to low. I am using a N/O switch to trigger the initial startup condition. I have been through multiple designs and they seem to work on paper but when built I cannot get them to work.

    Just seeing if anybody had any new ideas or approaches to help me think outside the box and get this thing working.

    Any help/comments are appreciated

    THANKS!
     
  2. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    Since this is a homework assignment, it would be best if you would post your effort to design the circuit and then the members here in the forum can assist you in refining your design.

    hgmjr
     
  3. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    Yeah I figured, I am at work and don't have access to cadence.
     
  4. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    Alright I will take a shot at explaining my last working design(on paper). I have 1 555 set up as a one shot with my output going to both #1 of a OR gate and the input CLK(falling edge) of my J/K FF. I have my J/K#1 set up to toggle on the falling edge of clock and its starting out with Q as high and /Q as low. My Q is going to #2 of my OR gate and #3(output) of my OR gate is going to brake. My Q/ of J/K#1 is going to a NOT gate then branching off to the input(clock down) of my second J/K#2 and to a small capacitor with hopes of re-triggering my 555 with J/K#1 toggles. J/K#2 is configured the same way as J/K#1(toggle, starting condition Q high, /Q low.) Q of J/K#2 is going to direction and /Q is tied back into pin 2(input) of 555 through a capacitor again with hopes of retriggering my 555 with /Q goes low.

    I am sure none of this makes much sense I am just trying to show that I HAVE tried a number of times to get this to work but just can't seem to, again any ideas?
     
  5. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    [​IMG]


    So ghetto I know
     
  6. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    Is there anything I can clarify on?
     
  7. samprots

    Thread Starter New Member

    Sep 21, 2009
    6
    0
    Thanks for all the help gee it sure helped!
     
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