I need some help w/this layout stuff. It seems that a "diffusion" layer isn't what I thought it was. Take a look at this NAND gate:

I notice that the larger "p-diffusion" and "n-diffusion" make a short between 3 contacts for the pmos and 2 contacts for the nmos. These are not supposed to be depletion type MOSFETs, so I would expect Vdd to be connected to a p-diffusion that is the source of the "B" pmos, then there should be the n-well under the "B" poly. Then another diffusion for both pmoses' drains. Then more n-well under the "A" poly, and a separate p-diffusion for the "A" pmos's source. Instead, what we have is a monolithic p-diffusion running between the 3 contacts and under the polies.
The nmoses have a similar problem. Not only that, but there's this gap between the polies over the n-substrate, so there's no chance of any field affecting that area. I am so lost.

 

The "channel" of the transistor is defined where the poly crosses the diffusion. This is a Poly gate, self-aligned, N-Well CMOS process. The P diffusion is where the two paralleled PMos transistors pull to the output of the NAND high if EITHER conducts. The Ndiffusion is where the two series NMos transistors pull the output to ground if BOTH conduct.

 

The "channel" of the transistor is defined where the poly crosses the diffusion. This is a Poly gate, self-aligned, N-Well CMOS process. The P diffusion is where the two paralleled PMos transistors pull to the output of the NAND high if EITHER conducts. The Ndiffusion is where the two series NMos transistors pull the output to ground if BOTH conduct.

Quite right, the gates are over the diffusions. But as I understand it, the gate should not be over the diffusion of an enhancement-type MOSFET. I've found many examples of this strange layout for bird's-eye layouts, but for cross-sections it's what it should be. Take this for example:

The gates are not over diffusions, but a substrate and a well.

 

Ask yourself how the n+ and P+ got there? What mask feature made the diffusions happen?

 

Ask yourself how the n+ and P+ got there? What mask feature made the diffusions happen?

How it got there? By doping silicon w/trivalent and pentavalent elements.

I spoke to my prof who explains that the convention in the esoteric VLSI sub-culture is that when you see a diffusion layer under a poly, it's not really diffusion, it's oxide followed by substrate or well. I don't know how they do it w/out going mad. I probably will on the midterm. She tried to explain the rationale behind that, but her first language isn't English and I can't understand anything she says. (Nor is it Teutonic, Romantic or Slavic)

 

Think of the process steps..

1. P-substrate
2. Poly is grown over p-sub
3. Then n+/p+diffusion step happens => this makes Source/drain and POLY as n+/P+ type( as poly will also be doped). The region under the poly is not doped as poly stops the ions.

Hope this helps.