trying to understand module

Discussion in 'Programmer's Corner' started by vead, Feb 26, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I am trying to understand how to write module for mico controller? (verilog)


    Modules

    - oc8051_acc: accumulator
    - oc8051_alu: aritmetic logic unit
    - oc8051_alu_src1_sel, oc8051_alu_src2_sel, oc8051_alu_src3_sel: alu source select modules
    - oc8051_b_register: sfr b register
    - oc8051_comp: compare
    - oc8051_cy_select: carry select
    - oc8051_decoder: main module, decodes instruction and creates control signals
    - oc8051_defines
    - oc8051_divide: alu submodule for division
    - oc8051_dptr: data pointer register
    - oc8051_ext_addr_sel: external address select
    - oc8051_immediate_sel: innediate data select
    - oc8051_indi_addr: indirect address select
    - oc8051_int: interrupt handling module
    - oc8051_multiply: alu submodule for multiplection
    - oc8051_op_select: operation select
    - oc8051_pc: program counter
    - oc8051_ports: port inputs and outputs
    - oc8051_psw: program status word
    - oc8051_ram_top: data ram
    - oc8051_ram_rd_sel: select address for reading from ram
    - oc8051_ram_sel: ram output select
    - oc8051_ram_wr_sel: select address for writing to ram
    - oc8051_regX: X wide registers (used to dely signal for 1 clock)
    - oc8051_rom: program rom
    - oc8051_rom_addr_sel: rom address select
    - oc8051_sp: stack pointer
    - oc8051_tc: timer/counter
    - oc8051_timescale
    - oc8051_top: top module
    - oc8051_uart: serial interface



    can anyone help how to assemble all submodule ?
     
  2. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    Why not choose a single one of them, define inputs and outputs and say what it should do, and then go from there?
     
  3. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    how is possible ?
     
  4. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Vead, please stop trying to do it this way. Learn this stuff the right way and understand the underlying concepts before you attempt such a project. Learn Verilog properly and you will be able to know how to connect the parts of a design.

    Doing it this way, assuming you actually compete it, will leave you with more questions than answers.

    This is not to discourage you from learning, but rather to discourage you from wasting your (and our) time.
     
  5. Papabravo

    Expert

    Feb 24, 2006
    10,136
    1,786
    Well...if you have the source file which defines the module, you open it up in a text editor, and you read it. You should look for the inputs, and the outputs, and the methods defined in the file to connect the inputs to the outputs.

    If you have a verilog or VHDL compiler then you can ask it to compile the module to see if it understands the text.

    In order to hook the modules together it would help to have an 8051 datasheet with a block diagram of the the various parts.

    That's how I'd do it if I were you.

    PS. The "top" module is likely to have the information about how all the sub modules are hooked together.
     
  6. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I don't know what exactly your mean. some member said me, learn basic things so I tried in this way , to learn verilog coding first we need to know how we can write module name and how we can write input output port so I did in this post. tell me, what I did wrong? I will leave it .
     
  7. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Learn Verilog before you attempt to make a controller in Verilog.
     
  8. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    I amn't asking for whole code I am learning verilog code I know little bit about. nobody can perfect , I know little bit like how to write verilog code for gates, memory, counter etc I did not understand some thing so I ask here
     
  9. Papabravo

    Expert

    Feb 24, 2006
    10,136
    1,786
    I may have misunderstood. Given the structure of your original post I may have assumed that you had the verilog source code for an 8051. If your original post is an enumeration of the modules you think will be in a verilog design for an 8051 then you are certainly biting off more than you can chew at the moment. You have to learn to crawl before trying to walk or run a marathon.

    The way you learn to write verilog is by reading what other people have written.

    Here is a tutorial in case you are lacking one
    http://www.ece.umd.edu/class/enee359a.S2008/verilog_tutorial.pdf

    Too bad it has a password that prevents you from printing a copy.

    *** EDIT ***
    The files listed in the Original Post have the same names as the 8051 project from the Open Cores website. You need to be able to read the verilog source in order to understand what is going on.

    http://opencores.org/websvn,listing...unk/rtl/verilog/#path_8051_trunk_rtl_verilog_

    Do you have one or more specific questions about this project?
     
    Last edited: Mar 4, 2014
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