Hello,
I am trying to simulate a JFET relaxation oscillator with TINA (complementary version) with no success. The circuit compiles fine but when I try to examine the output with the oscilloscope, I can't see the familiar psuedo-sawtooth waveform. Any thoughts on what I'm doing wrong?
Thanks

 

Your circuit appears to be missing a source of positive feedback. As it is, the RC network connected to the gate will simply charge until it reaches very near the postive voltage rail and there it will stay since there is nothing to discharge the cap to set things up for the next cycle.

hgmjr

 

So where should the positive feedback be? I thought the negative resistance characteristic of a JFET (and maybe this is where im wrong) will produce the sawtooth waveform. So after charging up to a certain point, the voltage of the RC network will drop.