Truth table of the circuit

Discussion in 'Homework Help' started by zulfi100, Jun 7, 2012.

  1. zulfi100

    Thread Starter Member

    Jun 7, 2012
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    Hi,
    Can somebody help me to write the truth table of a circuit having a NAND and an XOR gate ? One input of NAND is termed as 'a' while the output of NAND is termed as P which is one of the inputs of XOR gate. Other input of XOR gate is 'b' and its output is termed as Q. This output of XOR gate (i.e. Q) forms the 2nd input of NAND gate. Thus this circuit is similar to RS FF. Instead of two NOR gates,we have a NAND and an XOR gate. I saw this on the internet but I dont remember the link.
    I have found that:
    i) a=b=0, P=1 and Q=1
    ii) a=0 , b=1 then P=1 and Q=0 but I cant find out the values when:
    iii) a=1 , b=0
    iv) a=1, b=1.

    Thanks for reading my question.

    Zulfi.
     
  2. WBahn

    Moderator

    Mar 31, 2012
    17,716
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    Can you express, in words, why you are having trouble finding the output when 'a' is HI?

    If you can describe what is causing you difficulty clearly enough, I think you will start to see what the circuit is doing and why?

    In particular, you might perform the analysis of each condition twice. The first time, assume that Q is LO and then do the analysis to find out what Q is. Then redo the analysis assuming that Q is HI and find out what Q is.

    It might also help to consider a circuit that consists of nothing but a single inverter with the output fed back to the input. Then consider a circuit with two inverters where the output of the second is fed back to the input of the first.

    In light of this, as yourself what a NAND gate with one input tied HI looks like as far as the output as a function of the other input is. Then do the same thing for an XOR but consider what it looks like first when one input is tied HI and then when that input is tied LO.
     
  3. zulfi100

    Thread Starter Member

    Jun 7, 2012
    320
    0
    Hi,
    Thanks for your attention.

    If i take a=1 , i dont know which gate output should i find 1st. This is my problem but in any case i am getting Pn' and Qn' (i.e current output is inverse of previous output).

    For e.g if P=Q=0, and i find the output of XOR gate first then, Q=0 due to this output of NAND (i.e. P) is 1, due to this output of XOR (i.e. Q) is 1, due to this output of NAND (i.e. P) is 0 due to this output of XOR (i.e. Q) is 0 and so on???

    Similarly, if i find the output of NAND first, then P=1 due to this output of XOR (Q) is also 1 due to this output of NAND (i.e. P) is 0 due to this output of XOR (i.e. Q) is 0 and so on.

    For the other case (i.e. a=1 and b=1), i am facing race condition???
    So i would call it undefined case??

    Kindly reply me.

    Zulfi.
     
  4. WBahn

    Moderator

    Mar 31, 2012
    17,716
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  5. zulfi100

    Thread Starter Member

    Jun 7, 2012
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    Thanks. I checked it again and i found that output is not changing. Its similar to previous state. So is the following truth table correct??
    a b P Q
    0 0 1 1
    0 1 1 0
    1 0 Pn' Qn' (complement of previous state)
    1 1 Pn Qn (remembers previous state)


    Zulfi.
     
    Last edited: Jun 9, 2012
  6. WBahn

    Moderator

    Mar 31, 2012
    17,716
    4,788
    Yes.

    With both inputs HI, you have a circuit that is stable it two different states; thus it is known as a 'bistable' circuit and and is more commonly known generically as a latch.

    In practical terms, what you have is a gated oscillator. With 'a' LO, you can control the output directly with input 'b'. With 'a' HI, the oscillator runs when 'b' is LO and halts with 'b' is HI. However, you don't have any direct control over what state it will stop in; it will halt in whatever state it was in when you took 'b' HI.

    Another way of understanding the circuit is to consider that if you have a static control signal going to one side of an XOR gate, then with respect to the other input the output looks like a buffer if the control signal is LO and an inverter when it is HI.

    When input 'a' is LO, the feedback signal from Q doesn't matter and P is forced LO, making the XOR gate an inverter with respect to control signal 'b'. That explains the top half of the table.

    When control signal 'a' is HI, the NAND gate looks like an inverter while whether the XOR gate acts like a buffer or an inverter is controlled by input 'b'. If 'b' is LO, it acts like a buffer and so you effectively have the output of an inverter fed back to its own input. This is aboute the simplest oscillator around. In general, any time you take an odd number of inverters and connect them in a ring, you have a ring oscillator and many digital circuits that need a self generated clock use them. The more inverters in the ring, the slower the clock frequency. On the other hand, when 'b' is HI, the XOR gate acts like a buffer and now you have to buffers connected in a ring, which is bistable (as is an even number of inverters).

    So now imagine a ring formed by taking, say, ten inverters and one input of one XOR gate so that you have eleven gates in the ring, one of which has a control input. What value of that input will make the ring oscillator run and which will stop it?
     
    Last edited: Jun 9, 2012
  7. zulfi100

    Thread Starter Member

    Jun 7, 2012
    320
    0
    Thanks for this detailed answer. Right now i am not able to figure out the output. However, i would reply you in this regard.

    Thanks for your time.

    Zulfi.
     
  8. zulfi100

    Thread Starter Member

    Jun 7, 2012
    320
    0
    Sorry my friend, i cant answer your question. Its taking lot of time to understand your XOR analogy. I again thank you for your time.

    Zulfi.
     
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