I need help on how can i troubleshoot XOR logic gate, here is a situation:
View attachment XOR.bmp
We haven't learned Boolean algebra yet. I was trying to use step by step (A stuck Hi, A stuck Lo, B stuck Hi, B stuck Lo, etc) but I'm confused because it involves boolean. Can someone please help me approach.

 

What exactly is your question? Are you trying to figure why the XOR of A and B is incorrect?

 

What exactly is your question? Are you trying to figure why the XOR of A and B is incorrect?

Yes the question is to find what is wrong with this XOR gate (B is open/short, A is open/short?)

 

Are you trying to troubleshoot a real, actual XOR IC? If yes, which one and in which circuit is it implemented. How are you realising the connection with its inputs?

 

This is a book problem which basically asks to determine faulty gates but instructor asked to find possible problem that causes this problem.

 

I for once, have never heard of theory behind this subject. On my real life projects, rushed connections and wire windings are a constant headache. The ICs are rarely faulty.

 

I think the way to look at this might be: "How might inputs A or B look to the XOR gate such that is producing the output given?" In this context, since its a simple gate, your failure modes are probable either A stuck high, A stuck low, B stuck high, or B stuck low. Go through each of those cases, (leaving everything else unchanged) and see if you can figure out which one would produce that output...

 

The correct XOR would be 1000, you are missing a red x in your diagram. XOR Operation returns a 1 if A and B are different values, and a zero if they are the same value, if that helps.

In your scanned image, what is the green line, clock fed back from output, or other?

--ETA: Looks like the green line is the result of the XOR, which shows the original posts' outputs. Reading the output shouldn't happen exactly on the inputs leading/falling edge though (propagation delay). Still, in the cycle 2nd from right, input B is staying high (compared to inputs shown in diagram in OP). The XOR Gate is functioning fine. Garbage in, Garbage out.

Please post brighter images in future. Us old people can't see so good.

 

Take a clue from the shape of the inputs and outputs. Do you see one present at the output and at the input? Inverted perhaps?

Acting like an inverter for one input, instead of an XOR gate for two signals.

Almost anything is possible in the field, but there will be a standard set of faults that occur most often, and partial chip failure is not standard.

 

Take a clue from the shape of the inputs and outputs. Do you see one present at the output and at the input? Inverted perhaps?

Acting like an inverter for one input, instead of an XOR gate for two signals.

Almost anything is possible in the field, but there will be a standard set of faults that occur most often, and partial chip failure is not standard.

I think what their going for here is that Input A is shorted high, which would produce an inverted B. Given the scope of the question, I think that's the simple answer they want.

 

Thanks all for responses, I think I figured out what has been asked. Basically I would have to look at original gate's truth table and see what happens if lets in this problem in XOR gate A stuck Hi -> response should be Y=NOT(B), A stuck LO -> this is masking condition, B stuck Hi -> response should be NOT(A), B stuck Lo -> Masking condition, and Y stuck Lo or Hi -> not that definitely. SO out of all those conditions A stuck Hi is the one that causes problem so A is open or shorted to Vcc.