I am using 74126 as tri-sate buffer to drive a D Flip Flop clock input.
That is positive edge triggering of FF is controlled by buffer.
But the problem is that when buffer is in high impedance state, output should be Logic 0.
Does there need any 1K pull-down resistors to ensure Logic 0 state ?

 

Hex yes you should have a pulldown. High Impedance means the output is not DRIVEN to any particular level. It is not driven to 0, it is not driven to 1 it is not driven to Vcc/2. You should expect the DFF to go bats under these condition. Metastable would be an understatement -- high frequency oscillation would also be likely.

 

If you are driving another 74 series TTL chip, the pullup would have to be very low value to guarantee the input being below 0.6V

It's then unlikely that the buffer could supply enough drive to guarantee a valid high level. TTL outputs are good at pulling Low, not at pulling High.

You could put an invertor before the clock input, so you can use a pull-up resistor at the invertor input. That would give you a stable level that could be driven easily.

 

If you are driving another 74 series TTL chip, the pullup would have to be very low value to guarantee the input being below 0.6V

It's then unlikely that the buffer could supply enough drive to guarantee a valid high level. TTL outputs are good at pulling Low, not at pulling High.

You could put an invertor before the clock input, so you can use a pull-up resistor at the invertor input. That would give you a stable level that could be driven easily.

It is a good point. You see pulldowns in CMOS circuits. They are exceedingly rare in plain vanilla TTL. You need to find an alternative to this scheme.

 

See my application linked here.

To solve all these issues I will replace 74126 with 7408 AND gate.
One input of all AND gates will be from IC9 NE555.
Other input follows from NOT gates.
Now there is no problems of high impedance states. Thus positive edge
triggering for D Flip Flops.