Transistor electrical spec(2N3903)

Discussion in 'General Electronics Chat' started by Thevenin's Planet, Oct 24, 2011.

  1. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    Hi

    I have noticed that Transistor specs is not as versatile as it should be in regard to different biasing current or frequencies.It states specific operating points. 2N3903
    For example;To arrive at a hfe of 50 the Ic=10 ma and Vce 1Vdc.Which to me is strange because I have not come across a Vce at 1volt unless it's in saturation.Perhaps I am not understanding the stats correctly.I am assuming that I must adjust the base and collector resistors to get this Hfe=50 ? Or the input impedance or hie,Ic=1ma dcv,f=1khz.Futhermore,is the 1 khz is use with the shorting the output?I noticed that certain inputs or outputs of the transistor the signal is feed into.
    Also, is there a math calculation to determine the Ib quiescence point ,not the current follow thru the base resistors(Emitter grd, voltage divider input) but the one that comes out of the transistor base with out practical trials of measuring ?
     
  2. studiot

    AAC Fanatic!

    Nov 9, 2007
    5,005
    513
    Can you post the source for this?
    It is certainly unusual, since Vce will vary depending upon the rest of the circuit all at Ic=10mA.
     
  3. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    Here is a 2N3904 data sheet, possibly not the same one that the OP refers to, as at a quick glance I see references to VCE = 1V and 1kHz, but not the reference to "shorting". http://www.onsemi.com/pub_link/Collateral/2N3903-D.PDF

    Let's not imagine difficulties that don't really exist. The maker chooses to measure gain with a pretty low VCE, but whatever conditions are used are pretty arbitrary. At reasonable collector currents a typical transistor will not be saturated at 1V. A perusal of Figure 16 on Page 7 of the datasheet will show that in fact even at 100mA the 2N3904 is out of saturation by VCE = 1V.

    If you are familiar with BJT output characteristics, you will know that away from saturation the collector current (and hence the β) is usually a fairly weak function of VCE. It tends to rise a bit with VCE, I think mainly due mainly to something called the Early Effect*, but normally this is not dramatic.

    All of this is a long-winded way of saying that the β at VCE = 1V may be a bit down on that at higher voltages, but not so much as all that. In any case, β is such an unpredictable parameter that you should not even be trying to tie it down very tightly. Any design that requires that is heading for difficulties.

    *You can Google that bit for yourself.
     
    Thevenin's Planet likes this.
  4. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
     
  5. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
     
  6. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    The signal is being passed thru a step-down transformer to 12 volts and is reduced across a voltage divider network which reproduces about a 0.188 a.c.v.from the second resistor to ground, which is used as a test voltage to feed into a CE amplifier.I imagined that the transformer served as an isolation of some sort besides ac voltage reduction.
    Special instrumentation, what that could be? Additionally,The suppression of feed back you mentioned,is that what the OPEN CIRCUIT REVERSE TRANSFER PARAMETER IS USE TO MEASURE ,the h12 or hr.
     
  7. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    Why don't you post a schematic of whatever you are referring to. Trying to work that out from verbal descriptions is not easy.

    They could indeed want to short the output to ignore hr: no output voltage, so nothing to pass back. This short would need to affect signals only though, the DC collector current still needs to flow or the measurement becomes meaningless. A separate measurement would as you say provide a measurement of the reverse transfer.

    I would think that nowadays highly developed (and commensurately priced!) semiconductor characterization systems would be used for this sort of job.
     
  8. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    here it is.

    Rg1=10 K;Rg2=150 ohms;R1=100 k; R2=33 k; Rc=1 k; Re= 150 ohms; Rload=22 k;C1=22 microfarads; C2=10 microfarads.DC=9 DCV.
    The attempt to calculate the input resistance and output admittance in order that the correct capacitors can be use is the goal for this circuits.
    Seven micro amps(ac) are getting to base of transistor.Across VRg2=0.181 rms.with a 10 miroamps of current.The output across the Rload =36 microamps, Vbe=.660 DC. If I use 10k in Rload=72 microamps.
    Addionally,DC bias for IB=17.7 micro amps.(coming out of transistor)and VR2=1.461 DCV.About 63.5 microamps that passes thru R1 and R2.
     
    Last edited: Oct 29, 2011
  9. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    Why are you driving the amplifier from a mains transformer? Be that as it may, I don't think your results are quite right.

    In particular, the DC collector current looks to be be a lot bigger: you are going to get a bit less than a volt across the 150Ω emitter resistor. Here is the result of a LTSpice simulation using a 2N2222 transistor. Ic comes to about 5.6mA.
     
    Thevenin's Planet likes this.
  10. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    The mains is a good Sine wave and at this time,I don't have an ocilliator to get a test signal. Besides as you said it's very very slow,no heat problem or internal capacitance coming into existance.This might be transformed into an ocillator of some frequency.But I got to clear the matter of input and out impedances.
    Ltspice might not be taking consideration of real silicon material because I(Rg2) ,I have 1.17 ma with dignal meter,which is close to 1.4ma.
    Ib(Q1) my meter registered 7.5 uA instead of LTSpice 7uA.
    Ic= was biased at 3.83mA instead of the LTspice which is 5.6mA with a 1.2mA excursion.The load is 36 uA instead of the 50 uA
     
  11. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    I think that you may have not quite understood what I said. 60Hz IS such a low frequency that thermal effects could be an issue in really accurate work, but frankly I doubt that you would have to worry about that in your situation.

    You may have a somewhat lower gain transistor than was used in the simulation. I do not know what type you used: I used a 2N2222, a fairly typical device, but even transistors of the same type can have very different gains.

    LTSpice may not be the most accurate simulation in the world but normally you would expect a reasonable prediction of a transistor bias point. There is however an issue with your circuit which makes this difficult. The base bias resistors you have used are quite large in relation to the collector current expected, so the collector current will be quite dependent on β, which is generally not a good thing. Typically, the bias chain current might be set to about ten times the expected base current. Sometimes it is inconvenient to have the base resistors so low: there is a trade-off between bias stability and input impedance.

    Your transistor collector current is 3.83mA: if we assume your transistor has a gain of 100 times, the base current would be 3.83mA/100 or 38.3uA. The unloaded bias chain current however is 9V/133kΩ = 68uA, which is really too low for great bias point stability.

    To obtain a more predictable DC working point, you could reduce the base bias chain resistors by a few times, or alternatively you might like to increase the emitter resistance so that the emitter and collector current is as few times less.
     
  12. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    Is there a ratio of some sort of signal input(a.c.) to transistor's base current(DC),since the input signal would be supperimposed on the transistor's base biase current.I am aware that you mentioned that the unbaised chain current should be ten times the transistor base current,but the actual transistor's base current is what must be determined by trial and error or thru the Vce,Ib and Ic characteristic curve graph ,in which to get the Beta (DC).I have not seen any math calculation that would give the Transistor's base current.Although the calculation determines the current thru the unbaised chain current and voltage.
     
  13. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    The ratio of the AC (signal) to DC (bias) currents depends on how much signal you have in the first place. There is of course a limit if you do not want the signal to be clipped or limited, in that the signal must not be so big that it forces the current to zero, or perhaps reduces the voltage across the transistor too far. Before actual limiting occurs, you will expect the level of distortion to increase as the signal grows larger.

    Nobody would wish to use trial-and-error methods to design transistors for commercial systems, so more reliable methods of biasing transistors were worked out a long time back. This may be a new problem to you, but solutions were found to it more than 50 years ago. I learned about this when I was a teenager, nearly forty years ago.

    While the exact value of the base current will vary from device to device, if we start by deciding what collector current we require we can get an estimate of the likely range of base currents. These values can be used to determine the value of the base chain resistors, using the sort of rule-of thumb I mentioned earlier.

    As for solving for the base current directly, it is possible to use transistor model equations to solve for the bias point, either in a simplistic way using a simple model and linear simultaneous equations, or using more representative exponential models, normally with simulation software. It is not however usually necessary to do this to arrive at a reasonable bias set-up.
     
    Last edited: Oct 31, 2011
  14. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    This is a thread that was discuss not to far back about a.c. superimpose on a
    D.C..Using the Lt spice that is mentioned in this post. The Q1 base bias current has a 7uA (a.c.) excursion from 27uA (DC.) Data from a previous thread stated that,#1 If Vdc is greater than the peak value of a sine wave,the combine voltage or current is a sine wave that never reverses polarity. #2 And if Vdc is less than the peak value of a sine wave the sine wave will be negative during a portion of its lower half cycle.
    Can statement #1 be applied to the graph in this thread ? If so,can Zero be the limit before distortion of any kind take place? Regarding Lt spice for Ib,Positive=34uA(DC+a.c.) and Negative cycle is 21uA (DC-ac).Which leaves
    6uA from Zero or ground.If #2 in the above happens would that be considered as distortion ?
     
    • tn.jpg
      tn.jpg
      File size:
      2.4 KB
      Views:
      16
  15. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    In general, amplifiers are not perfectly linear, even for low-level signals. This results in some generation of distortion, which normally increases with the signal level, and typically rises dramatically when clipping* begins. *Clipping or limiting being the point where any current or voltage reaches its maximum or minimum value, preventing further change.

    You should understand that although limiting often marks the onset of very serious distortion, some degree of distortion is to be expected at lower levels. I am aware that I am repeating myself here, but this is a pretty fundamental point which needs to be understood.

    These remarks apply to Class A amplifiers like your example: other amplifier types such as Class B push-pull may also show a rise in distortion at very low drive levels, due to more complicated non-linearities.
     
  16. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    That is why my concern about the electrical stats that are given seems as though they are not considering the whole aspect of the biasing components around the active device (transistor).For example, the Ib in the LT spice in this post. The dymanic current would be 7uA and Rload would be 50uA, which the Beta= 50uA/7ua=7.1428.Once the the D.C. is
    stripped from the a.c. 50 uA is left going thru the load,50 uA x 22k =1.1 volts(a.c.),which I consider large reproduction for a second stage to handle for futher amplification.So do you think that the two generator resistors(Rg1,Rg2) should be considered as Source resistances to be in parallel to or in series to the bias resistors(R1,R2) to obtain input resistance(a.c.)?As is taught the input resistance and the input capactor
    forms a filter of some sort.Which can lead to attentuation of the input signal.
     
  17. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    The data-sheet information describes the performance of the transistor alone. It is the responsibility of the user to allow for the effects of external components, which are beyond the transistor manufacturers control. This must be so, as there are endless possible variations to the ways in which the surrounding circuitry could be designed. If you think about it, to take account of all possible external circuits the data-sheet for an ordinary transistor would have to be an impracticably large document.

    When calculating impedances to specify coupling capacitors, it is therefore necessary to consider the bias components, as well as the transistor's own impedances and those of the source and the load. Note that the resistors in a potential divider across a supply are indeed normally treated as being in parallel as far as AC impedance is concerned.

    The low frequency -3dB frequencies due to the coupling capacitors are given by f=1/(2*pi*R*C), where C is the coupling capacitance and R is the total resistance, Rg+Rin for the input, Rout+Rload for the output. This will involve a bit of work to combine all the relevant impedances.
     
  18. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    With this formula as the invert of what you stated above ,Xc1=1/2*pi*fc*Rin ;to get Rin,the source voltage divider resistors and the Bias resistors are in parallel with 26mv/Ic(DC) is what you are saying that must be done to get the overall input resistance in a.c. ?
     
  19. Adjuster

    Well-Known Member

    Dec 26, 2010
    2,147
    300
    Not quite: 26mV/Ic gives re, but the input impedance referred to the base is approximately (ß+1)*(re+Re), where Re is the external emitter resistor. Thus the input impedance of your stage would be approximately R1 in parallel with R2 in parallel with (ß+1)*(re+Re). This assumes that the external emitter resistor Re is not decoupled by a capacitor.

    The circuit you have posted has an external Re of 150Ω, which is considerably more than re assuming a few mA of collector current. This will lead to a relatively large input impedance to the transistor (≈16KΩ for β = 100), perhaps a lot higher than the parallel combination of R1 and R2, if these are chosen low enough to give bias stability. If Re were shunted by a large capacitor however, for the same gain the transistor input impedance might fall to less than 1kΩ, and the bias resistors might have a less dominant effect on the input impedance.
     
  20. Thevenin's Planet

    Thread Starter Active Member

    Nov 14, 2008
    183
    1
    I am imagining the 150 ohms is parallel to the C1(input cap) where the input voltage is coming from (and accordingly to my circuit the voltage is about 0.180 acv(rms)with a current going into the C1 about 11.8 uA,but
    entering the trasistor base at 7.5uA.which is an attenuation),should the Rg1 be considered in the calulation as part of the input resistance?
    The (B+1)(re'+Re) parallel to the transitor's biasing resistor(R1 and R2)which is in parallel to each other, the same what you have said, is the transistor input Z.Again,should the source Rg1 not be considered,since the voltage is taken off the Rg2 ??I am assuming that you use the above calculation to get 16 k input Z @
    b=100.I have not calculated this yet. Shunting or bypassing the Re to ground I have not considered at the moment.
     
Loading...