Problem: I have data sampled in an ADC at 337.5 MHz(actually it is sampled at 1335 MHz,but for sake of DDR3RAM i am slowing down the rate at which data comes out,using 1:2 demux provided within ADC) which needs to be written to a DDR3 RAM via a Virtex 7 fpga.(I am using Xilinx Vivado Design Suite)
My progress: To write data from Virtex 7 to DDR3 RAM, i used memory controller ip core given by vivado tool.After designing this,i need to give data from ADC to this memory controller module(some sort of interface).
So my question is, 1) can i use traffic generator provided by Xilinx for my purpose or do i need to write a new traffic generator for my purpose ?
2) Even with traffic generator i would require a user interface or the example traffic generator itself is sufficient ?
My progress: To write data from Virtex 7 to DDR3 RAM, i used memory controller ip core given by vivado tool.After designing this,i need to give data from ADC to this memory controller module(some sort of interface).
So my question is, 1) can i use traffic generator provided by Xilinx for my purpose or do i need to write a new traffic generator for my purpose ?
2) Even with traffic generator i would require a user interface or the example traffic generator itself is sufficient ?