Hello,

I am an embedded software engineer and I don't have much experience making decisions about cross talk between traces.

I am currently reviewing a design that has a TMS320F28335, a couple of data buses, I2C, SPI and multitude of other analog component. My concern is that there will be cross talk between the data bus or SPI traces. The data bus traces run together for about 2.5 inches and have a edge to edge trace spacing of 0.181mm. The SPI lines also run together for about 2.5 inches and have an edge to edge spacing of 0.181mm. The run of traces are embedded in the PCB with ground plane above the trace and a power plane below. The power plane is discontinuous with several different voltages (5V, 3.3V and etc.).

I am thinking the most important parameter is signal rise time, which has a maximum value of 8ns.

Could someone give me some suggestions on analyzing this situation.

Update: I forgot to say that I did do some analysis using http://www.ultracad.com/articles/formula.pdf and ltspice. I computed Co to be 3.9pF and then created an Ltspice circuit with a 3.9pF capacitor in parallel with a 1M connected (simulates load) to a PWL voltage source having a rise time of 8ns. The simulation resulted in a 1.6mA current for the duration of the rise time. The current seems quite large.

Thanks,
Steven

 

Here's a paper that should give you some insight into your design. To specifically answer the question of how much crosstalk you will get may require a circuit-board analysis program.

 

Thanks,

It gives me some extra info, however, not enough about crosstalk. However, the 2pF per inch was pretty close to the 3.9pF I computed.

Do you know of any open source tools that would help me do some of the computation?

Steven

 

........................
Do you know of any open source tools that would help me do some of the computation?

I've had no experience with them but perhaps one of these will help.