TO5 , Flat pack, dual in-line package packaging

Discussion in 'Homework Help' started by blackrider, Apr 22, 2005.

  1. blackrider

    Thread Starter Member

    Mar 19, 2005
    11
    0
    well i need some help ,i can't find what is the device packaging constraints of TO5 packaging Flat Pack packaging and the Dual In-Line packaging ,can anyone tell me what's the constrains of that? I am confusing of that, thx so much
     
  2. David Bridgen

    Senior Member

    Feb 10, 2005
    278
    0
    What do you mean by "constraints?"
     
  3. blackrider

    Thread Starter Member

    Mar 19, 2005
    11
    0
    limit. its mean about what is the bad of that packaging
     
  4. beenthere

    Retired Moderator

    Apr 20, 2004
    15,815
    282
    Hi,

    Your question is pretty broad. Plus TO-5 transistor cans have been replaces by the TO-39 package, and flat packs lost out to dual inline package many years ago.

    Probably the least good feature about dip's is poor heat dissipation. I've stuck on a PDF that gives ic package dimensions, if that helps.
     
  5. blackrider

    Thread Starter Member

    Mar 19, 2005
    11
    0
    thx beenthere,it will help me alot!!
     
  6. blackrider

    Thread Starter Member

    Mar 19, 2005
    11
    0
    erm i can know about the different of there 3 packaging?and compare it ,thanks
     
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