All About Circuits

Timing diagram problem with propagation delays?

Gonzalo Armbrust

Thread Starter

Gonzalo Armbrust

Joined Jun 28, 2015
16
I want some feedback to see if I completed the timing diagram for this problem correctly. Each gate in the circuit above the diagram has a 5 ns propagation delay, I have outlined my work in pen to make it a little easier to read ( work is in attached document)

initially w = x = y is equal to zero, i'm asked to find what V and Z would be after the changes at the corresponding nanoseconds
 

Attachments

You must log in or register to reply here.
Thread starter Similar threads Forum Replies Date
M 0 to 999 frequency counter using cd4060, cd4029, cd4543. Timing diagram help Homework Help 12
Pushkar1 [SOLVED]Timing diagram Microcontrollers 12
Y why timing diagram of combined SAR ADC is more efficient Analog & Mixed-Signal Design 7
Gonzalo Armbrust Timing Diagram problem: confused about changes from 0 to 1? Homework Help 1
N Timing diagram problem Homework Help 4
Similar threads
0 to 999 frequency counter using cd4060, cd4029, cd4543. Timing diagram help
[SOLVED]Timing diagram
why timing diagram of combined SAR ADC is more efficient
Timing Diagram problem: confused about changes from 0 to 1?
Timing diagram problem

You May Also Like

Top