timer help:

i am building a circuit in HDL verilog that changes a stop light depending on when cars are waiting or not at the other red light. the problem is i need a time delay in x amount of seconds, and the clock on the circuit board is works in 10.75Mhz. so i calculated it out to be about 25175000 clock cycles per second. im trying to develop a way that counts the posedge clock cycles and every time it reaches this high number a variable "tick" goes up by one. once tick equals the number of seconds i want, thats my time delay and the stop light changes. but im just making a short program with only one other variable to test out this timer but im have the most trouble. does anyone have any ideas?
this is my verilog code, it compiles fine but wont test right, so just use this as something to base your ideas off of, or just give me a completely new short thing of code to go off of with some explanations.

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module timingcircuit(a,clk);

integer clks,tick;
input clk;
output a;
initial clks = 0;
initial tick = 0;
reg a;
always @ (posedge clk)
begin
clks = clks + 1;
if( clks == 5)
begin
clks = 0;
tick = tick + 1;
end
if (tick == 5) // was originally tick == 25175000 but i had to make it //smaller for the sake of the testing program not going past one second. im // using quartus btw if that gives any ideas too
begin
tick = 0;
a = 1'b1;
end
else
a = 1'b0;
end

endmodule
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Thanks in advance
David