Timer circuit help

Discussion in 'The Projects Forum' started by jgerwitz, Aug 31, 2006.

  1. jgerwitz

    Thread Starter New Member

    Aug 30, 2006
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    I need help designing a circuit that will latch on to the carrier detect signal of a 232 circuit. The new circuit must hold the signal for 1.5 seconds. Here is the kicker. I need the logic levels of the input and output to be the same (i.e. input = high, output must be high; input goes low, the output goes low and hold for 1.5 seconds).

    I was thinking of using a 555 or 556 timer. Can anyone help with this project.

    Thanks in advance.
     
  2. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
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    When you say "low," do you mean "negative?" Or are you trying for some kind of lock-out application?
     
  3. jgerwitz

    Thread Starter New Member

    Aug 30, 2006
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    Not having done this very much and not being real familiar with eia-232, I think the low level will be around 0V. If I am correct EIA-530 levels are positive and negative. Please correct me if I am wrong.

    Thank you for your help!

    I am trying to monitor the carrier detect signal transistions during data communications and hold the DCD low for 1.5 sec. for the monitoring software.
     
  4. thingmaker3

    Retired Moderator

    May 16, 2005
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    I'm still not following. Sorry.

    Do you want a 1.5 second hi output each time your carrier detect changes state?
     
  5. jgerwitz

    Thread Starter New Member

    Aug 30, 2006
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    I hope I can make myself more clear this time.

    Here is my situation. I have a program that monitors the DCD (Data Carrier Detect) signal of an EIA-232 line to a special modem. When the phone connection drops the modem also drops the DCD signal LOW for approximately .5 seconds and then it goes HI again. The program that monitors this signal does so 1 time per second. To improve the odds of catching DCD go LOW, i need to put a hardware circuit between the computer and modem. When the DCD siganal goes LOW, i want to latch on to it and hold it for 1.5 seconds so that a software program, which poles the carrier detect signal every second, will see that the siganal has gone low.

    Think of what a 555 timer does built as a monostable. When the input goes LOW, the output goes HI and latchs it the for a time dependent on the resistor and capacitor in the timing stage. I need this to happen, however, the output must go LOW when the input goes LOW.

    I hope this clears things up and not made it more confusing. The concept is rather simple, however, putting my thoughts into written words is not simple sometimes.

    Thank you.
     
  6. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
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    Okay. I'm following now. Sorry for being so dense.

    Use an inverter on the monostable output. If you don't have room for a chip with six inverters, you could just use a switching transistor. The collector of a 2n2222 will go hi when it's base is low.
     
  7. Søren

    Senior Member

    Sep 2, 2006
    472
    28
    Hi,

    This will do it:

    Schematic
    [​IMG]

    Overlay
    [​IMG]
     
  8. jgerwitz

    Thread Starter New Member

    Aug 30, 2006
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    Soren,

    Can you explain how your circuit works and what it was originally used for? I'm not familiar with the IC 4093.

    Thank you.
     
  9. thingmaker3

    Retired Moderator

    May 16, 2005
    5,072
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    Good work, Soeren!

    When DCD goes low, o/p of IC1A is driven high. IC1B i/p is high until the capacitor charges enough to bring it below the schmidt trigger threshold. IC1B o/p will therefore be low for the same ammount of time.

    Datasheet for 4093: http://www.standardics.nxp.com/products/hef/pdf/hef4093b.pdf
     
  10. Søren

    Senior Member

    Sep 2, 2006
    472
    28
    Hi,

    Like a charm ;)

    Seriously... Not to ditch Thingmaker3's explanation, just to go a little "deeper":
    R1, D1 and D2 is input protection, since CMOS doesn't like it's inputs to go much above or below ist supply rails - sure, there is an equal circuit inside the beast, but since diodes usually fail short circuit, you don't want the internal protection to take a rap, as that would mean the death of the chip.

    C2 is merely decoupling and IC1C and IC1D, is just buffering the output, not really needed but just as well as leaving them static with their inputs connected to a supply rail.

    The work is done by the mono-flop (bistable multivibrator) consisting of IC1A, IC1B, C1 and R2.
    As T3 wrote, a low pulse on pin 2 will make the output high and since the cap was discharged initially, it's "other end" will go high as well toggling the output of IC1B (connected as an inverter).
    The output from IC1B keeps this state by holding pin 1 low, until the Cap is charged to about 2/3 of Vdd (the positive supply) and then reverts to its stable state.

    The formula is: t = ln(2) * R * C
    Ln(2) is about 0.693 or for a quick but rough calculation use 0.7
    R and C in Ohms and Farads respectively.


    Not "was" but "will be"... You descide, since you'll be the original user :)


    It's like a 4011 only with Schmitt triggers on its inputs.
    A 4011 would work as well.

    They are Quad 2 input NAND gate IC's (Quad = there are 4 gates to a package)
     
  11. pebe

    AAC Fanatic!

    Oct 11, 2004
    628
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    Just a point worth mentioning. The EIA spec for RS232 gives limits for a received high as +3V to +25V, and for low as -3V to -25V.

    Soren's output will only give a low of 0v. Although it will probably be OK, the circuit that it drives *may* need a -ve low.
     
  12. Søren

    Senior Member

    Sep 2, 2006
    472
    28
    Hi,

    Sure, just like any 555 circuit - wont be much of a matter to add (or use) a line driver though, or to just feed it from +/-6V if possible - but until such measures are established as needed... No point in overdoing things :).

    Anyway, EIA/TIA-232 is the protocol with the most often wrangled specs, eg. most laptops doesn't swing negative.

    The minimum limits is +/-3V at the receiving end allright, but I have never had any personal experience with equipment that wouldn't accept 0/+V only, only heard rumors of (badly designed of course) programmers for µcontrollers that wouldn't work with it.

    (The minimum at the transmitting end btw. is +/-5V).


    Not according to the OP as I read it, but should it be the case, it has a quick solution, but thanks for pointing it out :)
     
  13. pebe

    AAC Fanatic!

    Oct 11, 2004
    628
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    I have - long ago. An 8048 microcontroller txing to the serial port of a 386 based PC. Received data was erratic. Fitting a line driver fixed it.
     
  14. jgerwitz

    Thread Starter New Member

    Aug 30, 2006
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    0
    Thanks to everyone for your input

    Soeren, how did you get that cicuit created and designed so quickly? Excellent job!

    Thanks again,
    Jeff
     
  15. Spoggles

    Well-Known Member

    Dec 2, 2005
    67
    0
    Hello:

    Excellent information Soeren!

    I would just like to add one minor point. Hope it is not misunderstood as a 'nit'.

    The swithcing point of a typical 4093 is at the 40/60 % point. ie for a 10 volt supply the device would switch at 6 volts going 'hi' and at 4v going low.

    This would make the RC time = -ln(.60)*RC or 0.9 * RC.

    By the way, where could I find a timing diagram for a typical RS232 'handshake'. I understand the basic concept, but I have never seen a multi channel timing diagram for the process.

    Regards Spoggles
     
  16. Søren

    Senior Member

    Sep 2, 2006
    472
    28
    Hi,

    Goes to show how seldom this problem shows, wouldn't you say ? :)
     
  17. Søren

    Senior Member

    Sep 2, 2006
    472
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    Hi,

    After 4 decades with electronics and 2 decades with CAD, anyone should be able to :)

    Thanks :)
     
  18. Søren

    Senior Member

    Sep 2, 2006
    472
    28
    Hi,

    Perhaps I had my head a bit too deep in the 555 at the time of writing, but the 40/60% only counts for devices from some manufacturers, saying eg. 30/70% would be just as valid


    Apart from the fact that your calculator is obviously is playing a trick on you ;) I'd really like to see how you arrive at such numbers from your 40/60% idea ??


    Well, what do you mean exactly ? Just a graph showing the sequence in which it happens or what ?
     
  19. Spoggles

    Well-Known Member

    Dec 2, 2005
    67
    0
    Soren:
    I am sorry, I got the relationship 'upside down'. It should have been -ln(.4). -ln (10v-6v)/10v.

    -ln {(Vps-Vth)/Vps}. Of course the threshold for devices will vary, I was just pointing out that it probably would not be 50% -ln (10v-5v)/10v (.693).

    As far as the RS232 thing, yes a graph showing all the players would be great.

    Thanks
    Spoggles
     
  20. pebe

    AAC Fanatic!

    Oct 11, 2004
    628
    3
    Not necessarily. It hasn't happened again because ever since I used a MAX232 convertor.
     
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