Time step too small problem in LTSPICE

Discussion in 'Programmer's Corner' started by lklopes, Jul 12, 2016.

  1. lklopes

    Thread Starter New Member

    Jun 1, 2016
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  2. WBahn

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    I can't open the PDF file from the external site and I'm not going to open archives from unknown sources. You might take a screen shot of the schematic and post it here (after adjusting the size to something reasonable).

    Usually the time-step too small error is a result of the failing to converge. This can be caused by a few things. An input that changes too fast is a common culprit. Floating nodes (nodes without a DC path) can also cause problems.
     
  3. lklopes

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    Jun 1, 2016
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    Here are the screenshots of the original schematic and my LTSPICE project
     
  4. Alec_t

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    It will also help if you post your .asc file here.
     
  5. lklopes

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    Jun 1, 2016
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    The .asc file is here. All the .lib files used to import models are in the .rar file that I posted.
     
  6. WBahn

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    If that is a pulse source down in the lower-left corner, what are the rise and fall times on it?
     
  7. lklopes

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    Jun 1, 2016
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    1p second for each
     
  8. ci139

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    Jul 11, 2016
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    disable too fast voltage and current changes (insert small resistances (mΩ) , avoid small inductors(also Resistors that have inductance at high frequency(kΩ)))

    stabilize your grid (bigger or fine tuned capacities to feed lines)

    vary simulation time parameters

    vari simulation options
     
    Last edited: Jul 12, 2016
  9. ci139

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    Jul 11, 2016
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    if you use digital inverters then they have specified output voltage and no much limiting output resistance (as if you use a different supply for each)
    what you want to do is somewhat complex - uncouple the digital inputs using voltage dependent voltage sources and uncouple the digital outputs using voltage controlled switches (2 one for Vdd one for Vss (or GND if so)) (specifying the apropriate output resistance for - about 1kΩ for CMOS logic)
     
  10. ci139

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    Jul 11, 2016
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    the digital part does not seem to cause the problems . . . so ignore modifying digital

    ? the upper LT1762 ? it's IN to GND seems negative -40V ??? near startup (using alternate solver + some minor modifs. near all 3 voltage sources to make it run over 120+ns -- i don't quite grasp what it should do) then gets +100mV (it is possible to load the grid into normal op.-g voltages and then go with warm start ... if you know what they are ...)

    ? the optos have 1 to 4 N/C:N/C ?? there's no floating node error yet?

    i believe it can be simulated with reasonably powerful computer at reasonable time
     
  11. ci139

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    Jul 11, 2016
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    i degraded your circuit but it runs with 1ns timing - i donno if it's for any help
     
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