VGS = 3V
Vcc = 10 V
R = 1KOhm
VDS = 7V
iD = 3 mA

How does one, from these data, decide the threshhold voltage for this PMOS?

 

I see NMOS on the diagram and Vgs(off) is around 1.5V

 

Right it's an NMOS. I thought when the arrow points "out" it's PMOS and when it points "in" it's NMOS but apparently it's only like that in some symbols, and here it's the other way around. Very logical... NOT.

 

Right it's an NMOS. I thought when the arrow points "out" it's PMOS and when it points "in" it's NMOS but apparently it's only like that in some symbols, and here it's the other way around. Very logical... NOT.

The symbols are quite logical, as long as you understand what they are telling you. Look carefully at where the arrow is pointing to/from and you will see the difference. In one case it's pointing from the channel to the source, in the other, it's pointing from the bulk to the channel. Each symbol is using a different aspect of the physical FET device to indicate the polarity.

 

So what does the arrows represent actually, in either case?

For a) The arrows could be viewed as the direction electrons are attracted (or repelled), i.e. for NMOS electrons go to the left, thereby creating an N-channel

For b) The arrows could be viewed as ?

 

In bipolar transistor the arrows "show" the direction of a holes (positive charges). The conventional current flow.
But in MOS usually the arrow in bulk show electron current flow.

 

But in MOS usually the arrow in bulk show electron current flow.

That's correct for b) but not for a). So it's not really logical.

 

For case A we have "electrons" arrow (from "minus" to "plus").
For case B we have a positive charge flow arrow (conventional current flow).

 

For case A we have "electrons" arrow (from "minus" to "plus").
For case B we have a positive charge flow arrow (conventional current flow).

That's what I mean. The arrows points to two different things in each case (a and b). It's not logical. Logical would have been if the arrows would be refering to the same thing in both symbols

 

So what does the arrows represent actually, in either case?

For a) The arrows could be viewed as the direction electrons are attracted (or repelled), i.e. for NMOS electrons go to the left, thereby creating an N-channel

For b) The arrows could be viewed as ?

The arrow has to serve two purposes. First, it has to identify the polarity of the device, but second it identifies the source terminal, as opposed to the drain.

You have a similar situation in a BJT where the arrow not only identifies the polarity, but the emitter terminal, as opposed to the collector. For a BJT, the arrow represents the base-emitter diode.

In (a), the arrow represents the bulk-channel diode and the source is identified by being tied to the bulk side of that diode. In single MOSFETs, the source and the bulk are generally tied together in metal. But in integrated MOSFETs this is generally not the case because the buik is shared by multiple transistors (perhaps all of them of a particular polarity, such as all NFETs in an N-Well process) which would make it impossible to put them in series.

So you can't use a symbol that has the bulk-channel diode tied to the source, which means that it can't serve the purpose of identifying the source terminal. You then have two options. For many CMOS designs, there is no distinction between the source and the drain -- the device is truly symmetric and either terminal can act as the source terminal. In these situations, you can simply break the connection in the symbol to the bulk-channel diode and have a four-terminal symbol. You can't just do away with the diode symbol as you have to connect the bulk to something (floating bulks are not a good idea). But in many designs you connect the NFET bulks to Vss and PFET bulks to Vdd. If you are connecting them to a global node, you can embed that in the symbol netlist generator and leave out that diode completely. But now we have lost our means of indicating the polarity of the device. Hence the symbols in (b), in which the arrow is analogous to the BJT arrow. When there is no gate bias, there is no channel and the drain/source terminals are separated by bulk. In an NFET, the bulk is p-type and the source/drain regions are n-type, so you have a pn junction diode from the bulk to the source and that is what the arrow represents. For a PFET, the bulk is n-type and the source/drain regions are p-type, so you have a pn junction diode from source to bulk. Note that the FET involved may or may not be symmetric, but in general a FET will operate with either terminal acting as the source. The same is true of a BJT, but it is almost universal that a BJT connected with collector and emitter terminals swapped will behave markedly different, while that may or may not be the case with a MOSFET.

As for (c), that is generally used in logic circuits. In these circuits, the bulks are generally tied to the supplies on all transistors, so there is no need to show the bulk-channel diode. The devices are also almost always symmetric, so no need to distinguish source from drain. The bubble on the PFET gate is a "logic" bubble, indicating that you turn the transistor on, i.e., close the switch, by applying a LO logic level to the gate, while the NFET is turned on by applying a logic HI to the gate, hence no bubble.