# Three stage Asynchronous counter design

Discussion in 'Homework Help' started by ham3388, Aug 11, 2016.

1. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
Hi every one....
Im doing a distance learning course " Digital and Analog Devices and Circuits " .
Im stuck on the following question because I dont where from to start.
My confusion:
The counter outputs are 3 only, Q1 , Q2 , and Q3 but the logic outputs are 4 , A,B,C and D.
The truth table is not a Natural binary table.
So far I have not seen a 4 bit table with only 3 output of a flip-flop.
Could you please guide me to understand the question and help me to find the correct solution .

2. ### ericgibbs AAC Fanatic!

Jan 29, 2010
2,597
394
hi,
Those 3 output states can assume 0 thru 7 combinations.
E

File size:
7.5 KB
Views:
7
3. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
I am sorry, but really did not get what you mean?
With 3 output we can have only a scale of 8 counter but the truth table given is not a scale of 8 table.

4. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
the truth table is of 4 bit

5. ### WBahn Moderator

Mar 31, 2012
18,087
4,917
Add three columns to the table for Q1, Q2, and Q3 and you will see that your table really only has eight rows.

6. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3

Let us go step by step so I will be able to understand the things better.
Let us to clear the first point.
Where D has come from?

7. ### ericgibbs AAC Fanatic!

Jan 29, 2010
2,597
394
hi,
As suggested add the binary counter sequence.
'D' is simple, ref image, you complete the remainder.

How many bits change in the Table for each clock pulse.?

E

• ###### Image1.gif
File size:
24.1 KB
Views:
7
ham3388 likes this.
8. ### crutschow Expert

Mar 14, 2008
13,505
3,376
But it only has 8 unique states.

ham3388 likes this.
9. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
One thing got clear for me, the table has got only 8 unique states
But still not understanding the D logic at all.
I think my knowledge about counter designing is too poor.
I need more guidance. I'm trying to find some more worked examples about designing asynchronous counter but not getting. I facing a tough time right now.

10. ### ericgibbs AAC Fanatic!

Jan 29, 2010
2,597
394
ham3388 likes this.
11. ### WBahn Moderator

Mar 31, 2012
18,087
4,917
You have two things to design -- the "Counter" (which uses sequential logic) and the "Logic" (which does not).

You can tackle them separately. Break problems down into smaller chunks that can be solved one chunk at a time.

First tackle the counter. What if you were just given a problem to design a counter that counted pulses modulo-8, meaning that after the seventh pulse it wrapped back around to zero. Could you do that? If so, then do that. Don't even think about the "Logic" part of it until you have the counter done and working.

ham3388 likes this.
12. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
To eric:

Thanks Eric. ....
I went through the pdf , the truth table of Johnson counter using 4 flip flops was similar to table 1 and it is a syncrononous counter.
Here in the question a 3 stage asynchronous counter is given but with a similar truth table.
Do you suggest to use 4 flip flop counter?
Is that you mean?

Cheers

To WBahn :

Thank you very much.
Based on my knowledge and capability I designed the following counter. I guess the counter will reset after the count 8 automatically because it can not go beyond that.

Cheers

13. ### absf Senior Member

Dec 29, 2010
1,493
374
You need to tie KA, KB and CLR to '1' as well.

Last edited: Aug 12, 2016
14. ### absf Senior Member

Dec 29, 2010
1,493
374
Wait a minute. Wasn't your assignment said to use D flip flop?

Did you try your circuit in post #6 in the lab or using a simulator?

Allen

Last edited: Aug 12, 2016
15. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
Hi Allen. ...
No, I'm studying by distance learning
I have PSpice but don't know to use it much.

16. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
So do you think the above cicuit is correct?

17. ### ham3388 Thread Starter Member

Jul 3, 2012
97
3
I meant the one on post 6.

18. ### absf Senior Member

Dec 29, 2010
1,493
374
No, I'm afraid post 6 circuit is not going to work....

Check out the examples here.

Allen

Last edited: Aug 12, 2016
ham3388 likes this.

Jul 3, 2012
97
3
20. ### absf Senior Member

Dec 29, 2010
1,493
374
Yes, that should work. Now you have completed part a) of your assignment. Take a closer look at part b) and design a logic circuit that would convert 3 bit binary counter output to the pattern of the truth table.

Allen