The unusual problem with two capacitors

thatoneguy

Joined Feb 19, 2009
6,359
From looking at the graph of the solved problem with only one resistor, the dashed line appears to be the voltage the system "levels out" to. This would imply that E is a voltage source.

The solution, in non-math speak, is that C1 charges through R1 to E volts when the switch is connected so the left hand side is the complete circuit.

When the switch state is changed, R1 and the voltage source are completely removed from the solution.

At the switch change, the capacitor, charged to E, will discharge through the "leaky" capacitor C2, with R2 being the leakage.

The end Voltage after a period of time will be zero, with all energy dissipated by R2.

Does this make sense, or am I on the wrong track before I go further?
 

t_n_k

Joined Mar 6, 2009
5,455
The other important point to consider is that we on the forum haven't had the experience of attending MrRockchip's lectures / classes on this subject material.

His professor / teacher may well have been at pains to point out that these examples are of a generic nature - enabling one to give a consistent methodology or strategy for solving problems of this particular type.

I can well imagine a introductory statement like, "Ladies & gentlemen, please keep in mind that ideal capacitors don't exist in isolation of energy dissipating elements (e.g resistors) and that this analysis implicitly assumes the presence of such elements ...."
 

JoeJester

Joined Apr 26, 2005
4,390
Here is the simulation almost as drawn from the OP's original post.

The modification was the switch, which I used two timed switches to achieve the charge time and switch to the additional capacitor || resistor circuit.

Q = CV so Q will be 0.000005 prior to the Switch being thrown to the opposite position. Once thrown, adding the other capacitor and resistor combination, almost instaneously, V will decrease ... V = Q / C as C increased with the parallel capacitor. In my example, I used two 1 uF capacitors so V had to decrease to one-half and then decay expotentially.

If I graphed just the few microseconds around the switch point, the resultant graph would have followed the math. The sampling error caused the lower than expected voltage.
 

Attachments

Last edited:

Thread Starter

MrRockchip

Joined May 25, 2010
18
The voltage on C2 would be given by

\(V_{2}(t)=E \frac{C_{1}}{(C_{1}+C_{2})}[1-e^{-\frac{(C_{1}+C_{2})t}{RC_{1}C_{2}}}]\)

as t tends to ∞

\(V_{2}(inf)=E \frac{C_{1}}{(C_{1}+C_{2})}\)
But V1 and V2 (after switching the key) should tend to 0 as t tends to ∞ !
(according to the JoeJester's picture in the previous post - after 10 ms)
 
The solution to the circuit in post #12 would make sense if the top of C1 were permanently connected to the top of E, and if E were a voltage source, not a current source.

Then when the switch is thrown, the effect is to connect C2 in parallel with C1, with E still connected. Then, as time passes, the combination of C1 and C2 will be charged up to the final voltage that existed on C1 just before the switch was thrown, which is just the value of E.
 

t_n_k

Joined Mar 6, 2009
5,455
But V1 and V2 (after switching the key) should tend to 0 as t tends to ∞ !
(according to the JoeJester's picture in the previous post - after 10 ms)
The result I gave in that post was with respect to your post #12 rather than the original problem you posted at the very beginning.

This is one of the problems that occur as discussion starts to wander all over the place - we end up at crossed purposes and not always working off the same page or on the same problem.

In your original problem [post #1] I believe the final solution for the output voltage would be

\(U_{_{1}}(t)=U_{C_{2}(t)}=E\frac{C_{1}}{C_{1}+C_{2}}e^{\frac{-t}{R_{2}(C_{1}+C_{2})}}\)

which does indeed go to zero as t goes to ∞.

This all hinges on a number of side issues as to the nature of the source type (voltage or current - seemingly a voltage), interpretation of the switch function and so on.
 
Top