Hello,
I did not expect that my first participation here is going to be something about R-2R. Sorry for that!

The question that bothers me about this R-2R ladder circuit is about its linearity. Is it linear? Many documents say that it is linear. But, i think it is not. Look, i know that we can apply the superposition technique in it, but this does not mean that it is TOTALLY LINEAR.

Here it is my proof:
I made 4 bits R-2R ladder for a DAC system. I supplied it with 9 volts battery. The calculation shows that i should expect 8.4 if all the bits are on. Okay, suppose now i want instead a supply of 9.3. Can't I just subtract the 0.3 from the output to get the same as the 9.0's output? What do you think?

In fact, i tried that, and i got the same but it was off by 0.025.
and in another case working with different bits .. it was off by 0.1 volts.

It is supposed to be non linear because the output is always expressed as Vin/(2^n) = Vout where n is the bit we work with. So, if we add 0.3 to Vin, it does not make sense to get Vout+0.3 ???? so why is it linear ?

 

Since the use of superposition requires linearity....

Why do you think you should be able to subtract 0.3 from the output?

Linearity says that if the input is doubled, the output is doubled, right?

So if the input is multiplied by 1.0333, then the output will be multiplied by 1.0333.

 

Perhaps it would help you see that the R-2R ladder is linear by first being very explicit about the input/output function that is used.

Vout = f(Vin) = ????

 

Your apparent definition of linear and thus your "proof" is not correct.
A little thought on the relationship between a resistive divider's input and output voltage should help you understand that.

 

There are three inherent error sources in an R-2R ladder, and either one can be mistaken for non-linearity. The easy one is the tolerance of the resistors. If you have an 8-bit ladder, then each 1-bit change represents about 0.4% of the output. If you are using 5% tolerance resistors, the output linearity will measure very poorly. Another error is the effective resistance of whatever is switching the resistors, relative to the size of the resistors themselves. Finally, there is what is called quantizing error. For each individual digital value controlling the ladder, the output voltage or current is allowed to be within a range of values so long as it does not deviate from the theoretically-perfect output value by more than the equivalent of 1/2 least significant bit. If you step through each digital value, measure the output values, subtract the theoretically perfect values, and plot the differences, it will probably be a very jagged line. Within limits- this is acceptable even though the error plot does not appear linear.

ak

 

Since the use of superposition requires linearity....

Why do you think you should be able to subtract 0.3 from the output?

Linearity says that if the input is doubled, the output is doubled, right?

So if the input is multiplied by 1.0333, then the output will be multiplied by 1.0333.

Yes, you were right. I think what I did is not a property of linearity.

I should evaluate the additional 0.3 volts in a separated calculation - like what i did for 9.0 volts- by using the equation vin/2^n and then subtract what I got from that equation from the 9.3 calculation. --> this is the correct property.


Thank you very much

 

Your apparent definition of linear and thus your "proof" is not correct.
A little thought on the relationship between a resistive divider's input and output voltage should help you understand that.

Yeah my proof is wrong because my definition is wrong. Right!

But even with using calculating what i need properly- based on the fact that if f(x)=y and f(x) is linear then f(x+a)= y+f(a)-, i was also off by 0-0.1 range volts.

So, i think it still linear but you know the practical limitations prevent the perfection !

 

There are three inherent error sources in an R-2R ladder, and either one can be mistaken for non-linearity. The easy one is the tolerance of the resistors. If you have an 8-bit ladder, then each 1-bit change represents about 0.4% of the output. If you are using 5% tolerance resistors, the output linearity will measure very poorly. Another error is the effective resistance of whatever is switching the resistors, relative to the size of the resistors themselves. Finally, there is what is called quantizing error. For each individual digital value controlling the ladder, the output voltage or current is allowed to be within a range of values so long as it does not deviate from the theoretically-perfect output value by more than the equivalent of 1/2 least significant bit. If you step through each digital value, measure the output values, subtract the theoretically perfect values, and plot the differences, it will probably be a very jagged line. Within limits- this is acceptable even though the error plot does not appear linear.

ak

Yeah. I did my calculations yesterday based on the fact that f(x+a)=f(x)+f(a) and i got better results but not perfect. So, of course, there are always practical limits. I thought that 0.1 volts off data is not acceptable but according to what you said .. i think that thing is reasonable now.

You explained the error sources from 3 different points of view especially the switch resistance .. i had not thought of that !!! Thank you very much.

 

The point I was trying to make is that changing a 9V input by 0.3 volts in a linear system will change the output for each of the 2^N output values by 0.3/9 = 3.33% not 0.3V, which is what WBahn was telling you.
That has nothing to do with any inherent inaccuracies in the R-2R component values.