Thanks for the quickie....but i didn't get it completely......when you said connect the enable pin all together ....it means i can connect all of them high or VDD ....( it is same as giving all of them logic one ) .

And if i understood you correctly .....you asked me not to connect anything to parallel inputs of counter ....it is not necessary , is that correct ?


I will attach my data sheet pdf , thanks a lot for your time .....

"learning is fun "...

 

Thanks for the quickie....but i didn't get it completely......when you said connect the enable pin all together

No, connect all Enable "P"'s together (CEP, Pin 7).
Additionally, you connect the Enable "T" (CET, Pin 10) to pin 7 of the first counter.
If they are held below 0.8v, the counters will not count.
If they are held above 2.8V, they will count.

The TC (pin 15) output of the first counter is connected to the CET (pin 10) of the 2nd counter. The TC of the 2nd counter is connected to the CET of the 3rd counter, etc.

ALL clock pins (CP, Pin 2) are wired together. This is where you apply your signal generator's square wave to cause the counters to count.

If you wish to use the reset function, ALL reset pins (pin 1) are wired together. You can connect these to the output of one of the counter's Qx pins if you wish for the count to reset early instead of "rolling over". If you do not wish to use the reset function, you don't have to connect them to anything.

....it means i can connect all of them high or VDD ....( it is same as giving all of them logic one ) .

Yes.
If they are 74LS161 IC's, the correct terminology is Vcc. Vdd is for MOS/CMOS/DMOS.

And if i understood you correctly .....you asked me not to connect anything to parallel inputs of counter ....it is not necessary , is that correct ?

Yes. Unless you want to use the preset function and set the counters to a specific value, there is no need to connect anything to the Px inputs.

 

Thanks a lot, I will connect everything as you said. I hope it works for testing the DAC.

regards
shantanu