testing and fault in vlsi system?

Discussion in 'General Electronics Chat' started by vead, May 30, 2014.

  1. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    How many type of fault can be occur in VlSI circuit ?

    when we make chip It may be work or it may be fail due to some fault
    chip may be fail due to fabrication process
    chip may be fail due to circuit connection
    chip may be fail due to packing

    how we will detect fault in chip and what is fault model in vlsi system?
     
  2. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    VLSI design are automated

    customer requirement
    specification
    functional design (by using hardware description language )
    digital design (using gate level model )
    circuit level (using gate are implement using transistor )
    layout design
    fabrication process ( layout is convert into real chip )
    chip manufactured

    suppose this chip is not working
    how we will determine fault in chip
     
  3. tshuck

    Well-Known Member

    Oct 18, 2012
    3,531
    675
    Many chips have a JTAG boundary scan that allows one to control the I/O of the FPGA in circuit.

    Many designers include a Built-In Test(BIT) that allows the design itself to validate that it can operate as intended in the field.
     
  4. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    fault may be occur during fabrication , during connection , during packaging

    Q1 If fault is present in component , which testing method we will use to detect fault ?
    Q2If fault is present in interconnection , which testing method we will use to detect fault ?
    Q3 If fault is know, can we recover fault in chip ?
     
  5. vead

    Thread Starter Active Member

    Nov 24, 2011
    621
    8
    VLSI testing is process that is used to determine that chip is good or faulty

    VLSI chip is tested by test equipment and some test circuit

    can anybody tell me the example of some test circuit

    actually I am confused I don't understand that fault model and test circuit are different or same things
     
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