Hey guys, we just a practical to do in college and the whole class is completely confused as the lecturer would not/could not help us.

We had to demodulate an FM signal which was modulated by a DC signal using a Phased Locked Loop (PLL). The idea here was to increase the amplitude of the DC signal which would deviate the modulated signal from 20kHz up to the point where the output of the PLL would stop following the FM signal. Whats bothering me is, according to my lecturer, the PLL only starts following the FM signal at +-8kHz from 20kHz. I.e. starts around 28kHz and 12 kHz these values are supposed to be the point at which the PLL starts to LOCK. The lock then breaks at just over 10kHz on either side of 20kHz.
Whats confusing me is firstly, why must the PLL only lock at the above values? It makes more sense to me for the PLL to follow as much as it can.
Also, my telecomms board, my PLL was following EXACTLY right from 20kHz.
This is apparently wrong and i have no idea on how to rectify it???

 

Hello,

Can you post a schematic?
This will help to clearify your problem.

On PLL-circuits a lot is written.
See these results of the search of the EDUCYPEDIA.
Each result will give a page of the EDUCYPEDIA with lots of links.
http://search.freefind.com/find.htm...&n=0&_charset_=windows-1252&bcd=%F7&query=pll

Greetings,
Bertus

 

Hi Bertus, thanks for the reply. Well i'd happily give you one but we are using already made modulation "boxes" and all we really have to go by are the symbols on the board. I am in work now but i can give you the block diagram that i have when i get home.

 

Ok so enclosed is the block diagram. The telecomms boards we use just have just have these symbols on and all we have to do is effectively modulate by numbers.

Hope someone can make more sense out of it than i can

 

Hello,

The phase comparator gets 2 signals.
One from the manual controlled voltage frequency converter (Uf) and
one from the VCO (U2).
The output of the phase comparator is dependend on these two signals.
If there is a difference between the two input signals it will change the output voltage to change the frequency of the VCO to get equal inputs.
The output of the comparator is filtered, this is to have a reasenable reaction time (fast enough to follow, slow enough to eliminate disturbances).
There are two ranges as you discribed.
The lock-in range and the hold range.
The lock-in range is most of the time smaller than the hold range.
This has to do with the properties of the phase comparator and the VCO range.

I also attached a datasheet of the HEF4046, this is an PLL ic with a pretty explepantion on its function.

Greetings,
Bertus

 

ok i had a look at the datasheet but i still dont understand whats going on here.

According to the Analysis in my notes, the Voltage out of the low pass filter being fed into the voltage controlled oscillator varies with the waveform modulating the original FM signal. This would suggest that the PLL would need to follow the FM signal throughout the range of the FM signal for it to be effective. My lecturer told us that the PLL only starts to follow or "lock" with the FM signal about 8 kHz on either side of the undeviated carrier, in this particular case, 20kHz. So what about the frequencies between these values? for low voltage modulating signals, which wont deviate the carrier too much, the PLL doesnt follow them? The PLL here also stopped following the FM signal around 10kHz above and below the carrier. I.e. this is the fold frequencies.

What I saw on my particular lab was that the PLL followed the modulating signal exactly (or at least to the accuracy the frequency meters displayed) which my lecturer referred to as wrong. This appears to me to be working correctly? Is it not ideal to have a PLL follow the FM signal over its entire range?

Some of the other students in the class were able to measure the lock and hold frequencies like this:
The frequency discrepency (between the deviated FM signal and the PLL signal going into the comparator) was about 50 Hz up intil the locking frequency whereby the discrepence lowered to about 10 Hz.

Another thing which was causing great aggravation was when changing the dc voltage which changed the ffrequency deviation, as the dc voltage was lowered (going into the negative voltages) the frequency would go down from 20kHz then at around 13 kHz go up to 14kHz then go down again.I figured this may have been an artifact of the potentiometer but some of the other students had the same problem.

 

Hello,

In theory the PLL should lock-in at every frequency between 12 and 28 kHz in your case.
(the signal des not need to be on the edge of the range).
It should also follow a low frequency deviation, the demodulated signal will be small in this case.

Greetings,
Bertus

 

What you just said makes sense to me but apparently its not what i should be getting. Lock in only starts there and ends at about 30 and 10 kHz.

 

Hello,

Locking a signal sometimes can get problems when the phase is incorrect.
The phase comparator is trying to push the signal away in that case.

Greetings,
Bertus

 

Hey guys, we just a practical to do in college and the whole class is completely confused as the lecturer would not/could not help us.

We had to demodulate an FM signal which was modulated by a DC signal using a Phased Locked Loop (PLL). The idea here was to increase the amplitude of the DC signal which would deviate the modulated signal from 20kHz up to the point where the output of the PLL would stop following the FM signal. Whats bothering me is, according to my lecturer, the PLL only starts following the FM signal at +-8kHz from 20kHz. I.e. starts around 28kHz and 12 kHz these values are supposed to be the point at which the PLL starts to LOCK. The lock then breaks at just over 10kHz on either side of 20kHz.
Whats confusing me is firstly, why must the PLL only lock at the above values? It makes more sense to me for the PLL to follow as much as it can.
Also, my telecomms board, my PLL was following EXACTLY right from 20kHz.
This is apparently wrong and i have no idea on how to rectify it???

A lecturer/professor confused? This is impossible!

In any case, the lock range of a PLL is determined largely by the bandwidth of the bandpass filter. I don't think the lock point is as well-defined as your professor has implied.

In any case....if the difference in frequency between your reference and your feedback is greater than the bandwidth of the filter, your PLL will fail to lock. Now, you're probably curious about the LOW frequency aspect.

Since the feedback comparator is actually a MIXER, your reference oscillator and feedback are going to produce TWO output frequencies...a sum and a difference. One is an alias of the other (or for us old-school OF's an "image"). If you can't reliably separate your image from the "real" product, your PLL is going to be hopelessly confused....hence the LOWER frequency limit imposition.

Now, here's the beauty of the situation. Once the phase locked loop is indeed locked...the lower frequency limit is not an issue.....the image and "real" output frequencies are one and the same...only tiny phase differences.

Because of this...ALL PLL's actually have two modes....a "trying to get locked" mode and an actual, genuine, for-real locked mode. The parameters between these two states can be a real art form to optimize. If you need to do this FAST, topologies such as the FREQUENCY/PHASE locked loop are often implemented.

Hopefully I've been able to confuse you more than your professor.

eric

Eric

 

Since the feedback comparator is actually a MIXER, your reference oscillator and feedback are going to produce TWO output frequencies...a sum and a difference. One is an alias of the other (or for us old-school OF's an "image"). If you can't reliably separate your image from the "real" product, your PLL is going to be hopelessly confused....hence the LOWER frequency limit imposition.

Hi Eric, thanks for that reply and i think i did manage to follow what you are saying. OK so the hold frequency makes sense based on what you have said: if the frequency is too high, it will be filtered out but i am still confused about the "Phase lock upper" and "Phase lock lower frequencies" i.e. the frequencies the FM signal has to have before the PLL will "lock". I dont understand why there is this minimum frequency deviation from the carrier frequency and as i was sayin i plain didnt see it occurr at all in my lab. My PLL followed the FM signal exactly from the 20kHz to above and below 10kHz.

 

Ok i think i have finally found the answer i was looking for. The problem i had was that my lecturer led me to believe that the PLL cannot lock at low frequencies. I found a pdf on the net - an arrl article on PLLs which explains this quite nicely. What i think my lecturer was getting at is the "capture range" which is the range at which the PLL gets back into a locked stage, i.e. bringing the frequency closer to the center frequency such that the PLL locks again.

If anyone wants a read of this pdf its here: http://www.arrl.org/tis/info/pdf/0809071.pdf