Hi,
Can anyone help me explain why we have the state reset =0, q(n) = 0, q(n+1)=0 in the below picture?
Can anyone help me explain why we have the state reset =0, q(n) = 0, q(n+1)=0 in the below picture?
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It is a example in Verilog HDL: A Guide to Digital Design and Synthesis by Samir palnitkar.Nope. It seems to me that you have contradictory entries in the table (the middle line and the last line).
Where did you get the table from? If possible, ask your instructor what it is supposed to mean.
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