T flipflop from D flipflop and inverter

Discussion in 'Homework Help' started by anhnha, Aug 28, 2012.

  1. anhnha

    Thread Starter Active Member

    Apr 19, 2012
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    Hi,
    Can anyone help me explain why we have the state reset =0, q(n) = 0, q(n+1)=0 in the below picture?
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    Nope. It seems to me that you have contradictory entries in the table (the middle line and the last line).

    Where did you get the table from? If possible, ask your instructor what it is supposed to mean.
     
  3. anhnha

    Thread Starter Active Member

    Apr 19, 2012
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    47
    It is a example in Verilog HDL: A Guide to Digital Design and Synthesis by Samir palnitkar.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    I don't know if I have that particular text or not. But without looking at the entire context in which the table is given, my impression is that it is a mistake in which the author copied a table from earlier in the book and modified it but didn't delete that row.
     
    anhnha likes this.
  5. Georacer

    Moderator

    Nov 25, 2009
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    I agree with WBahn. It can get pretty frustrating when you read a badly revised edition of a textbook.
     
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