Synthesizable delay in Verilog

Discussion in 'Embedded Systems and Microcontrollers' started by Shagas, Jul 28, 2014.

  1. Shagas

    Thread Starter Active Member

    May 13, 2013
    802
    74
    Hello

    Can someone advise how to implement delays in Verilog?
    I've tried googling it and it either takes me to test benches or to some advanced papers which I don't understand.

    Do I have to implement some sort of "request -> counter -> permission" sort of thing to get a proper delay?
     
  2. JWHassler

    Member

    Sep 25, 2013
    201
    33
    It's a little more complicated than it looks.
    Here's a state-machine that steps through its sequence with each step taking a different number of clocks.

    Code ( (Unknown Language)):
    1. //-----------------------------------------
    2. // delay state machine
    3.  
    4. module State_Machine(
    5.     input    clk,            
    6.     input        [1:0]    In_Condition,
    7.     output    reg    [1:0]    Out_Condition
    8.  
    9.     );
    10. localparam    
    11. IDLE    = 3'd0,    //
    12. ST_1    = 3'd1,    //
    13. ST_2    = 3'd2,    //
    14. ST_3    = 3'd3;    //
    15.  
    16. // - - - - - - - - - - - - - - - - - - -
    17. // a state-machine
    18. reg [3:0]state;    // state-reg
    19. //- - - - - - - - - - - - - - - - - - - -
    20. // a delay-clock for adjusting time of states
    21. //   can be set to 1-7 clocks long
    22. reg [2:0]ticker;// for time delays
    23. wire TIMEOUT = (ticker == 3'h0);
    24.  
    25. always @(posedge clk) begin
    26.  
    27.     //------ delay-clock: if non-zero, it ticks down to zero ---------
    28.     if (ticker != 3'd0)    ticker    <=    ticker - 3'b1;
    29.    
    30.     // state-machine
    31.     case(state)
    32.         IDLE:
    33.             begin
    34.                 Out_Condition[1:0]    <=    '0;        // both go to zero in idle-state
    35.                 if (In_Condition[0] ) begin            //  when the first input goes high
    36.                     ticker    <=    3'd2;                //   ...set delay to 2 clocks
    37.                     Out_Condition[1:0]    <=    2'b01;    //   ... assert first output
    38.                     state    <=    ST_1;                //   ... go to state ONE
    39.                     end
    40.                 end    // of 'idle'
    41.  
    42.         ST_1:
    43.             begin
    44.                 if (In_Condition[1]&& TIMEOUT) begin//  when the first input goes high AND MIN DELAY ELAPSES
    45.                     ticker    <=    3'd3;                    //   ...set delay to 3 clocks
    46.                     Out_Condition[1:0]    <=    2'b10;        //   ... assert second output
    47.                     state    <=    ST_2;                    //   ... go to state TWO
    48.                     end
    49.             end    // of 'ST_1'
    50.         ST_2:
    51.             begin
    52.                 if ( TIMEOUT) begin                        // state two is ONLY a delay
    53.                     Out_Condition[1:0]    <=    2'b11;        // ... at the end of which BOTH outputs are asserted
    54.                     ticker    <=    3'd4;                    // ... another delay begins
    55.                     state    <=    ST_3;                    // ... and we go to state THREE
    56.                     end
    57.                 end    // of 'ST_2'
    58.         ST_3:
    59.             begin
    60.                 if ( TIMEOUT )                            // state three just delays, then goes to IDLE-state    
    61.                 state        <=    IDLE;
    62.                 end    // of 'ST_3'
    63.     default: state    <=    IDLE;
    64.     endcase
    65. end // always posedge clk
    66.    
    67. endmodule    
    68.  
     
    Shagas likes this.
  3. kubeek

    AAC Fanatic!

    Sep 20, 2005
    4,670
    804
    Best approach is to imagine how you would do it with real circuits, and then convert to verilog.
    So my approach would be an n-bit counter, with clock and reset inputs and an output.
    on each clock:
    When reset is low, increment the counter, then compare it with the timeout value. If you reach the timeout, set the output.
    When reset is high, set count to 0 and reset the output.
    Use the output to enable the execution of whatever you wanted to delay. You should be able to synthesize gated clocks for example.
     
  4. Shagas

    Thread Starter Active Member

    May 13, 2013
    802
    74
    Hmm yes I was planning to do it similarly , just wanted to check if there was some other way of doing it.
     
  5. Brownout

    Well-Known Member

    Jan 10, 2012
    2,375
    998
    You can chain some logic together and use their combined propagation delays. Since all modern design is synchronous these days, there is really no reason to do this.
     
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