Hi all,
I have the following code that gives me the correct output when I simulate it at the RTL level. But when I synthesize the gate level of this code even at 20 MHz it keeps going into the optimization phase for very long hours(18 hrs is what it has gone so far and then I ended the simulation i.e it gets stuck at this stage).
At 10 MHz, it generates the .mapped file of the code but then it does not get compiled in the master file containing the test bench, osu018_stdcells.v and .mapped.v . It shows 33 errors as : module *** has timescale but previous modules do not.
At 1 MHz, none of the above problems come and the code gets synthesized as it should. My doubt is that I synthesized the individual functions at 500 MHz and still the entire code does not get synthesized at 10 MHz.
Kindly tell me what could the problem be.
The extension for the codes is .v (not .txt) for dct.txt and test.txt
I have the following code that gives me the correct output when I simulate it at the RTL level. But when I synthesize the gate level of this code even at 20 MHz it keeps going into the optimization phase for very long hours(18 hrs is what it has gone so far and then I ended the simulation i.e it gets stuck at this stage).
At 10 MHz, it generates the .mapped file of the code but then it does not get compiled in the master file containing the test bench, osu018_stdcells.v and .mapped.v . It shows 33 errors as : module *** has timescale but previous modules do not.
At 1 MHz, none of the above problems come and the code gets synthesized as it should. My doubt is that I synthesized the individual functions at 500 MHz and still the entire code does not get synthesized at 10 MHz.
Kindly tell me what could the problem be.
The extension for the codes is .v (not .txt) for dct.txt and test.txt
