Synchronous counter with D flip flop help

Discussion in 'Homework Help' started by rocky86, Nov 29, 2010.

  1. rocky86

    Thread Starter New Member

    Nov 29, 2010
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    Hi guys i need help with this problem! is from my uni past year paper, reallx do not noe how to do!
    [​IMG]
     
  2. retched

    AAC Fanatic!

    Dec 5, 2009
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  3. rocky86

    Thread Starter New Member

    Nov 29, 2010
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    I understand the video, however i still do not noe how to solve the problem because it appear the sequence of the states is different due to the condition on the question!~
     
  4. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
    6,357
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    Try drawing the gates from the outputs to the inputs for Da, Db, and Dc using the logic specified. Then work through it as shown in the video.
     
  5. blah2222

    Well-Known Member

    May 3, 2010
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    33
    This isn't too bad because they are D flip-flops and they are all synchronized (clocks are all the connected). They are all positive-edge triggered. So to simplify all this, they are all going to change at the same time.

    Initial Conditions:
    Qc = 0
    Qb = 0
    Qc = 0

    So, since these are positive-edge triggered D flip-flops, every positive edge of the clock will cause all the D's to pass their values to the Q's.

    So, the next rising edge will cause:
    Qc = Dc
    Qb = Db
    Qa = Da

    The D values are calculated from the previous Q values.

    Dc = Qa + Qb
    Db = Qa'Qb + Qc'
    Da = QbQc

    So given that the first sequence is 000, the following will occur before the next rising edge of the clock:

    Dc = 0 + 0 = 0
    Db = 0'0 + 0' = 10 + 1 = 1
    Da = 00 = 0

    These values are then passed to the Q's on the next rising edge of the clock, then the process continues.

    Try it out yourself, but this is what you should get:

    000
    010
    110
    111
    101
    100
    000
    ...repeat

    So now that we know the pattern, you can find out what the output would be at any amount of rising clock pulses.
     
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