Synchronous Counter using T Flip-Flops

Discussion in 'Homework Help' started by jegues, Oct 23, 2010.

  1. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
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    Design a four-bit synchronous counter with parallel load using T flip-flops.

    See figure attached for my attempt.

    I hooked up a standard counter using T flip flops and AND gates and then for the parallel load I created a load input that runs into 4, 2-1 MUX's.

    If load = 0 then it will spit out the output of the preceding flip flop.

    I.e. y0 = q0, y1= q1 etc...

    If load = 1 then it will load the data accordingly.

    I.e. y0 = w0, y1 = w1 etc...

    How does this look?

    The solution listed doesn't use any multiplexers, but this is how I understood it so this is what I did.

    Let me know what you think!

    Thanks again!
     
  2. Georacer

    Moderator

    Nov 25, 2009
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    No, this is not what a counter with parallel load is.

    The idea is to have a counter on which you can load any number and continue counting from then on.

    This can be a little tricky on a T-FF synched counter, as you have to give the right excitation on the FF when loading to get the desired state.

    An overview of the circuit is this:

    The FFs will be in series, just as you drew. But the T-inputs won'd be hardwired. Instead, they will be selected by the Load signal (through a MUX possibly). If S=0, the counting will go as normal. If S=1 you must isolate the T-FF and give it the correct excitation to make it load the number you want (Hint: XOR gate).
     
  3. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
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    I could barely redraw it (in another format) with the solution sitting infront of me. If I asked to do something like this on a test I don't see how I could manage. The only possible way I think I could do it is if I had it memorized before hand.

    Seems pretty hopeless right now...
     
  4. Georacer

    Moderator

    Nov 25, 2009
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    It's not so hard to remember. See the 3rd schematic in this page: http://www.allaboutcircuits.com/vol_4/chpt_11/3.html

    The answer you posted, differs from the simple synchronous counter only in the regulation of inputs.

    When enable is 1, it works exactly as the counter in the e-book. This configuration, yes, you have to remember it by heart.

    When enable is 0, instead of the standard input from the AND gates, you use the input from the XOR gates. The use of the XOR gate can be explained by a truth table but it is better to remember it too.

    Finally, the selection between the two is done by a 2-to-1 MUX. That doesn't need too much gray matter to find out.

    It is true however that you can't think of this configuration all by yourself, if they ask it for the first time. So, read a lot and be prepared.
     
  5. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
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    After studying the circuits you've mentioned I've got a question.

    If I remember the Up/Down counter for JK flip flops then from there I can construct either an UP counter or a Down counter by controlling the Up/Down control signal.

    For example, If I wanted a down counter.

    After thinking about, I guess I don't need the AND gates in there either.

    Is this thing working?
     
  6. Georacer

    Moderator

    Nov 25, 2009
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    Compare it to the Down Counter provided in the same link. Do the FF input function look the same to you?
     
  7. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
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    I didn't want to design it as the Down Counter provided it in the link. I wanted to implement it from the Up/Down Counter provided in the link, because then if I could do that, I would only have to commit one to memory.

    Then if I'm asked for a Down Counter I can simply tweak my Up/Down Counter(In my memory) into simply a Down Counter.

    It's probably not going to look like exactly like the solely "Down Counter" in the link but it should function the same I think.
     
  8. Georacer

    Moderator

    Nov 25, 2009
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    You can use the Up/Down schematic. The problem is that you used it wrongly (does that word even exist?). Notice that the output of each NOT gate goes to the next FF too, not only the one immediately after.

    Removing the OR gate was correct.

    In the end you have no choice but end up with the "Down Counter" schematic. There isn't an alternate form in the simplest level.
     
  9. jegues

    Thread Starter Well-Known Member

    Sep 13, 2010
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    Thank you for pointing this out Georacer. I was drawing my Up/Down Counter incorrectly and this was leaving me with mistakes in my Up Counter and Down Counter derivations. I think I've got it all sorted out now. (See figure attached)
     
  10. Georacer

    Moderator

    Nov 25, 2009
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    Don't forget to put a 1 in the first FF.
     
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