Design a four-bit synchronous counter with parallel load using T flip-flops.
See figure attached for my attempt.
I hooked up a standard counter using T flip flops and AND gates and then for the parallel load I created a load input that runs into 4, 2-1 MUX's.
If load = 0 then it will spit out the output of the preceding flip flop.
I.e. y0 = q0, y1= q1 etc...
If load = 1 then it will load the data accordingly.
I.e. y0 = w0, y1 = w1 etc...
How does this look?
The solution listed doesn't use any multiplexers, but this is how I understood it so this is what I did.
Let me know what you think!
Thanks again!
See figure attached for my attempt.
I hooked up a standard counter using T flip flops and AND gates and then for the parallel load I created a load input that runs into 4, 2-1 MUX's.
If load = 0 then it will spit out the output of the preceding flip flop.
I.e. y0 = q0, y1= q1 etc...
If load = 1 then it will load the data accordingly.
I.e. y0 = w0, y1 = w1 etc...
How does this look?
The solution listed doesn't use any multiplexers, but this is how I understood it so this is what I did.
Let me know what you think!
Thanks again!
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