synchronous active low reset D-flipflop

Discussion in 'The Projects Forum' started by sara yu, Dec 1, 2015.

  1. sara yu

    Thread Starter New Member

    Sep 24, 2015
    HI all,
    I need help in understanding synchronous active low reset in D-flipflops. As I get it,state of the flipflop is dependent on clock cycle(synchronous) and rising clock edge(active) but what is low here? reset is resetting the flipflop to zero. If we have to draw this D-flip with transmission gates(4), does this schematic include a two input AND gate(D, reset) or (d, reset_n) before the transmission gate?
  2. ian field

    Distinguished Member

    Oct 27, 2012
    Set and reset inputs on flip-flops are usually unconditional - that is they usually override any other input conditions.

    Synchronous usually refer to outputs state of change - usually they all change state at once (synchronously) in response to a clock event.
  3. Papabravo


    Feb 24, 2006
    Since you are designing this at the silicon level there are two possibilities.
    1. Synchronous D-Flip-Flop, with an asynchronous RESET
    2. Synchronous D-Flip-Flop with a synchronous RESET
    Either one would be a valid device. The way you've chosen to run the words together has created at least on ambiguity, and we are all about precision on language.
  4. AnalogKid

    Distinguished Member

    Aug 1, 2013
    Sorry, no and no.

    1. In this case, synchronous is a description of a requirement for the reset action. It means that the ff is *not* reset the instant the reset input changes to the active state. Resetting occurs *only* when the clock edge happens. So for this ff to be reset, two things must be true at the same time: a) the reset input is in the active state right before the clock edge; b) the clock edge happens. An asynchronous reset means that the ff is reset instantly when the reset input changes, even if it is in the middle of a clock cycle. Each type of reset can be useful in different situations. The 74161 is a synchronous counter with an asynchronous active low reset, while the 74163 has a synchronous reset.

    2. In this case, "active" is not describing the clock or the clock input. It is part of "active low", the logic state of the reset input. A reset input can be high or low, and either state can be used to reset the ff. This description means that the low state is the state that causes a reset, not the high state. As above, either type of reset can be useful. The 4017 has an asynchronous active high reset while the two counters mentioned above have active low resets, one synchronous and one not.

    sara yu likes this.
  5. sara yu

    Thread Starter New Member

    Sep 24, 2015
    Thank you all for helping out.I clearly get it now. This is part of my project and could you please correct me if I am wrong with my design of D-flipflop in the following file or image
    .(D- flip with 4 transmission gates in a shift register with synchronous active low reset,that works on the rising edge of the clock) so that I can finish the shift register(SIPO).
    Thank you again Analog kid, your explanation is lucid.
  6. sara yu

    Thread Starter New Member

    Sep 24, 2015
    I got the flipflop design done and it is working but when I connect three similar flipflops in series with parallel outputs and with a NAND in the front with two inputs D, reset_n and run the simulation I am not seeing the output changing with D at the rising clock edge.Output should not change at reset high.As I want an active low reset in 3- bit SIPO shift register, but it is not. I do not know why the output change is not in accordance with input at that moment at only rising clock edge,instead it is changing with every rising clock edge with a little delay(in the timing diagram).

    I think I am wrong with NAND. As I understand it , a 3-bit shift register with synchronous active low reset working at a rising clock edge should have Q(output) 1 only when D is 1 and reset is 0 in all the other 3 cases Q should be 0 at a rising clock edge and the output is shifted with every input bit(D) and 3 bits are supposed to display at the same time( in the circuit design)

    I will also try including clk complement at every transmission gate

    Can anyone suggest something that might make it work and correct me if my understanding is wrong.Please find the images attached with the circuit design and timing diagram.

    Thank you,