Another solution (with absolutely no pulse shaving) is to use a positive edge-triggered D FF with the long pulses going to the D input and the short pulses inverted and going to the CLK input (you could skip the inverter if you used a negative edge-triggered FF).
The FF Q output goes to one input of a two input AND gate with the short pulses going to the other input.

The AND gate will then open at the fall of the first short pulse after the long pulse goes high.
This insures the first short pulse is always complete.

The gate closes at the fall of the last short pulse after the long pulse goes low.
This insures that the last pulse is also not truncated.

The one possible disadvantage to this solution is that there can be nearly one short-pulse-period delay before the first short pulse appears at the gate output, depending upon the relative phase between the short and long pulses.

 

But don't leave the D and CLK inputs floating. The sim might take it, but you can't expect reliable operation in the real world if you do that.

Hooking up power and ground will help also.

There is some more circuitry to add.

 

@electronice123
OK, this is what your schematic should look like. I added the stop logic. Why don't you put this into your sim program and show the Q output of the 74ls74 relative to A1 and A2.

I'm not seeing how this will work.

It will only clear the pulse when both A1 and A2 are LO. So when A2 is HI, the A1 pulses never get cleared.

If will only set the output on the falling edges of the A1 pulses that occur within the A2 window.

Have a missed something, such as a change in spec?

 

Hooking up power and ground will help also.

There is some more circuitry to add.

Yeah, I chose not to mention the power/ground because sometimes, in some simulators, that causes problems because there is a global logic power/ground and because that is something that is seldom overlooked in going from the sim to the actual circuit (though there have certainly been exceptions!).

 

A1 is a square wave, A2 may change in order to allow A1 to maintain equal pulse lengths on every pulse.

lestraveled,

I put that circuit in multisim exactly as shown and guess what? I'm only seeing A2 at Q?

 

Here is @crutschow design. (I hope I converted text to schematic correctly. It looks good to me.)

Sim this up and see how it works.

 

Look carefully and you will see that you haven't put it in exactly as shown.
You are sending A1' to both of the logic gates. Is that what LesTraveled is showing?

 

I'm not seeing how this will work.

It will only clear the pulse when both A1 and A2 are LO. So when A2 is HI, the A1 pulses never get cleared.

If will only set the output on the falling edges of the A1 pulses that occur within the A2 window.

Have a missed something, such as a change in spec?

The circuit's not complete.
The FF output goes to a two input AND gate with the other input being the short pulses.
The AND gate output is the gated signal.

 

A1 is a square wave, A2 may change in order to allow A1 to maintain equal pulse lengths on every pulse.

lestraveled,

I put that circuit in multisim exactly as shown and guess what? I'm only seeing A2 at Q?

Guess what, you are seeing exactly what you should see. this circuit only generates the enable gate. You need to add the AND gate to complete the circuit.

Edit: is my internet connection that slow?????

 

Here is @crutschow design. (I hope I converted text to schematic correctly. It looks good to me.)

Sim this up and see how it works.

I think this should work and I don't see any potential glitch problems. There one very critical race, but it is pretty safe to assume that it will be won in the direction needed. There is another less critical race, but it should also be won in the direction needed.

 

.....................There is another less critical race, but it should also be won in the direction needed.

Considering the speed of the logic and the operating frequency of A1/A2, there will be no measurable negative impact.

 

Here's my simulation.

 

Considering the speed of the logic and the operating frequency of A1/A2, there will be no measurable negative impact.

The operating frequencies of A1 and A2 don't affect the race. It's the delay along the two paths between A1 and the AND gate. Unless the straight line connection goes out to Timbuktu and back or is highly inductive, it is a safe assumption to assume that the direct path will win the race. But such race conditions need to be identified and considered in asynchronous (including gated-clock) designs.

 

Here are both schematics. Take your pick. (I think crutscow won.)

 

@electronice123 @crutschow

This was fun. We should do it again sometime.

 

If you use NAND gates as shown in my sim then you only need two chips.

 

If you use NAND gates as shown in my sim then you only need two chips.

Go ahead crutschow, rub it in.

 

Ok, that works.....Man that is tricky stuff....Hopefully I'll understand it better when I get further along in y EE degree...Right now I've only had the first class. Thank you all for your help, I really appreciate it!

It would have taken me days to figure that one out

 

@electronice123 @crutschow
I want you to analyze both approaches. My approach was more systematic. The start and stop blocks were broken up to show function. crutschow approached it like the seasoned and cunning engineer he is. You need to understand this language. You will not just be learning facts, you will be building new pathways in your brain. (Don't worry about the facial twitch, it will go away. )

 

@electronice123 @crutschow
I want you to analyze both approaches. My approach was more systematic. The start and stop blocks were broken up to show function. crutschow approached it like the seasoned and cunning engineer he is. You need to understand this language. You will not just be learning facts, you will be building new pathways in your brain. (Don't worry about the facial twitch, it will go away. )

Will do, thanks for the advice....

I tried the NAND version and I'm not getting the same results? I get a high output during the gate time instead of a low?


UPDATE: Never mind, I see what I did wrong.

Thanks again everyone, this forum is awesome!