The trick is to have the gating function go high before the first short pulse and low after the last short pulse to avoid shaving the pulses or generating glitches.
I believe I have a solution for that using a D-FF and a couple gates, but I won't post it until the OP has made a further stab at the solution.

Very good. It would be interesting to see all of the solutions we come up with. We are such creative devils here at AAC.

 

@electronice123
Is there are problem if 20 to 50 nano-seconds were shaved off of the first or last pulse??

 

I believe I have a solution for that using a D-FF and a couple gates, but I won't post it until the OP has made a further stab at the solution.

I think a FF is wrong, due to the asynchronous nature of the two signals. I think Les is on the right track using Set/Clear, though I might opt for a simple R-S latch.

 

I think the interesting side of this circuit will be getting rid of ambiguous states when edges occur at the same time. Still it may not be a problem if the TS can stand loosing a few tens of nano-seconds here and there.

 

I've got a project I don't know how to go about. I have two signal generators (A1 and A2). Each will output a different frequency and each frequency is adjustable. One frequency (A2) will always have a longer pulse length than the other. I need the longer frequency to gate the shorter one but in a way that does not change the pulse length of any of the shorter pulses. I also need this to happen no matter how much I change the frequencies. I have attached a picture showing what I am trying to do. You can see that the OUT pulses all have the same pulse length even when the other pulses A1 and A2 might cut them short if I used logic gates.


Initially I thought an 4071 OR gate would work, but once I simulated it in multisim some of the leading pulses were cut short and some of the trailing pulses were cut short.


How can I get the result I am looking for?

74120 Pulse Synchronizer?

 

I think the interesting side of this circuit will be getting rid of ambiguous states when edges occur at the same time. Still it may not be a problem if the TS can stand loosing a few tens of nano-seconds here and there.

Hmmm.... guess I have to take back what I said about the FF, as using latches isn't really any better.

 

I've got a project I don't know how to go about. I have two signal generators (A1 and A2). Each will output a different frequency and each frequency is adjustable. One frequency (A2) will always have a longer pulse length than the other. I need the longer frequency to gate the shorter one but in a way that does not change the pulse length of any of the shorter pulses. I also need this to happen no matter how much I change the frequencies. I have attached a picture showing what I am trying to do. You can see that the OUT pulses all have the same pulse length even when the other pulses A1 and A2 might cut them short if I used logic gates.


Initially I thought an 4071 OR gate would work, but once I simulated it in multisim some of the leading pulses were cut short and some of the trailing pulses were cut short.


How can I get the result I am looking for?

Some others may have already mentioned this, but two questions that your original diagram leaves open:

1) What should the output look like if A2 goes HI in the middle of an A1 pulse?

2) Your final pulse on the output is a pulse on A1 that started well after the pulse on A2 ended? So what determines whether a pulse on A1 is copied to the output? Clearly it isn't as simple as any A1 pulse that started while A2 was HI.

 

I think the interesting side of this circuit will be getting rid of ambiguous states when edges occur at the same time. Still it may not be a problem if the TS can stand loosing a few tens of nano-seconds here and there.

The TS is going to have to deal with that part of the specification -- namely if the behavior is different if A precedes B than it is if B precedes A, what is the behavior if A and B occur at the same time and what does "at the same time" mean? For something like this, it usually comes down to something like, "if A and B occur within x nanoseconds of each other, they are deemed to be "simultaneous" occurrences and the behavior is undefined." This is essentially the same as defining a setup and hold requirement.

 

Some others may have already mentioned this, but two questions that your original diagram leaves open:

1) What should the output look like if A2 goes HI in the middle of an A1 pulse?

2) Your final pulse on the output is a pulse on A1 that started well after the pulse on A2 ended? So what determines whether a pulse on A1 is copied to the output? Clearly it isn't as simple as any A1 pulse that started while A2 was HI.

The above questions were asked and resolved in posts #6/#7 and #23

 

I'm under the opinion that if electronics can power computers cell phones and everything else this is probably a pretty measly task.

So I'm looking at the datasheet for the 74LS74. I can see and understand what the NAND is doing before the preset, but when looking at the truth table for the flip flop is where I get confused......What do I use for the other inputs?

What signal do I need to use for the clock. It confuses me because the datasheet says if either the preset or reset is low then it resets the output regardless of the logic levels of D and CLK?

Q will only be high under two conditions-With preset low and reset high (don't care on D and CLK) and with preset high, reset high, CLK on rising edge, and D low.....WHEW, this is confusing.

@electronice123
Is there are problem if 20 to 50 nano-seconds were shaved off of the first or last pulse??

Yes, the reason why I need all the pulses to be the exact same length is because they will be used to drive an impedance matching circuit.

 

The above questions were asked and resolved in posts #6/#7 and #23

Thanks.

The solution as I see it would be to use RS latches and place the system in armed and disarmed states. My first off-the-top-of-my-head list of states would be DISARMED (output=LO), PREARMED (output=LO), ARMED (output=LO), and ARMED (output = HI).

 

I'm under the opinion that if electronics can power computers cell phones and everything else this is probably a pretty measly task.

Not necessarily. As soon as you start throwing around requirements that pulses have to be the exact same length, you are imposing constraints that no cell phone has to achieve.

So I'm looking at the datasheet for the 74LS74. I can see and understand what the NAND is doing before the preset, but when looking at the truth table for the flip flop is where I get confused......What do I use for the other inputs?

What signal do I need to use for the clock.

If you don't have a suitable clock signal, then you need to either use these devices that are intended for synchronous operation in an asynchronous way (and lots of demons lie along that path) or design an asynchronous circuit from the get-go (still some demons, but they are at least out in the open).

Yes, the reason why I need all the pulses to be the exact same length is because they will be used to drive an impedance matching circuit.

No two pulses are every exactly the same length. You need to specify how close to the same length they need to be. It's hard to imagine that two pulses that differ by 1 femtosecond are going to matter. But how about 1 nanosecond? 10 nanoseconds? How close is close enough.

 

Not necessarily. As soon as you start throwing around requirements that pulses have to be the exact same length, you are imposing constraints that no cell phone has to achieve.



If you don't have a suitable clock signal, then you need to either use these devices that are intended for synchronous operation in an asynchronous way (and lots of demons lie along that path) or design an asynchronous circuit from the get-go (still some demons, but they are at least out in the open).



No two pulses are every exactly the same length. You need to specify how close to the same length they need to be. It's hard to imagine that two pulses that differ by 1 femtosecond are going to matter. But how about 1 nanosecond? 10 nanoseconds? How close is close enough.

Honestly I'm not sure how close they'll need to be. The high frequency will be between 8kHz-20kHz while the low between 800Hz-2kHz.
Never thought about how tight the tolerances will need to be. I'm just afraid if the pulses are too long or too short them impedance change will effect my circuit. My components have rather large reactance values (60k-100k ohms) so perhaps a few 10s of nanoseconds wouldn't change much...

 

@electronice123
What is the frequency range and pulse width of A1 and A2??

 

@electronice123
The period of 20 Khz is 50 uS. 50 nano-seconds is 1000 times less that that. I suspect that a pulse width change of 50 nano-sec. will be below your ability to notice it.

Can you say how these pulses are being used? How is the impedance being measured?

 

Pulses are used to drive an impedance matching transformer to near saturation then shut off before saturation occurs.

Just a project, so what about the FLIP FLOP.....

You mentioned before using a NAND gate with a 74LS74?

 

@electronice123
What is the frequency range and pulse width of A1 and A2??

A1 range: 8kHz-20kHz
A2 range 800Hz-2kHz

 

@electronice123
OK, this is what your schematic should look like. I added the stop logic. Why don't you put this into your sim program and show the Q output of the 74ls74 relative to A1 and A2.

 

But don't leave the D and CLK inputs floating. The sim might take it, but you can't expect reliable operation in the real world if you do that.

 

A1 range: 8kHz-20kHz
A2 range 800Hz-2kHz

But what about the pulse width? Are these square waves, or pulse trains?