Synchronize clocks in VHDL

Discussion in 'Programmer's Corner' started by Tom H, Dec 20, 2004.

  1. Tom H

    Thread Starter New Member

    Dec 20, 2004
    1
    0
    Hi,

    I have 3 times incomming data with clock signal, all at 40MHz but I cannot know the skew. This can be different for the 3

    Is there any way I can synchronize them all on another 40MHz clock signal, without risk of glitches or invalid data??

    Any suggestions are more than welcome

    Regards

    Tom H
     
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