I'm trying to estimate switching losses in my design, and I am hung up on estimating the "Miller plateau." I need to know at what voltage the Miller plateau occurs and I'm not sure how to do that.
Gate charge graphs on FET datasheets show where the Miller plateau is, but the graph is at a specified drain current. Is it true that the voltage of the Miller plateau varies with drain current, and if so, how would one go about finding out what this voltage is at other drain currents?
One of my ideas was that I could use the transconductance of the FET to tell me what gate voltage is needed to support a specific drain current and could figure out the Miller plateau voltage from that. But I'm not sure how the transconductance itself varies; it also appears to vary based on drain current?
The ultimate goal is to come up with a way to figure out the switching time when the FET is supporting a significant \(I_d\) and \(V_{ds}\). Maybe there is a different way to do this than how I'm attacking it...
Any help or insight would be much appreciated.
Gate charge graphs on FET datasheets show where the Miller plateau is, but the graph is at a specified drain current. Is it true that the voltage of the Miller plateau varies with drain current, and if so, how would one go about finding out what this voltage is at other drain currents?
One of my ideas was that I could use the transconductance of the FET to tell me what gate voltage is needed to support a specific drain current and could figure out the Miller plateau voltage from that. But I'm not sure how the transconductance itself varies; it also appears to vary based on drain current?
The ultimate goal is to come up with a way to figure out the switching time when the FET is supporting a significant \(I_d\) and \(V_{ds}\). Maybe there is a different way to do this than how I'm attacking it...
Any help or insight would be much appreciated.
