Switching a 9V JFET with 5V CMOS logic?

Discussion in 'General Electronics Chat' started by dfro, Jan 10, 2011.

  1. dfro

    Thread Starter Active Member

    Feb 6, 2006
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    Anybody have any ideas on the best way to switch a 9V JFET with a 5V CMOS MCU?

    What interfacing BJT or CMOS chip should I use?

    Thanks,
    Dave
     
  2. beenthere

    Retired Moderator

    Apr 20, 2004
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    Could you say something about the function? What is the JFET and what current is being handled?
     
  3. Ctenom

    Member

    Nov 1, 2010
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    I don't have much experience in electronics but if you have a 9v supply in the circuit couldn't you use a reed relay or a solid state relay?
     
  4. Kermit2

    AAC Fanatic!

    Feb 5, 2010
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    You need a source of 9 volts in the circuit somewhere to generate a 9 volt gate drive signal.

    You could add another battery, or regulator and activate an everyday average transistor to send its voltage to the mosfet gate.

    Very sloppy solution. Better solution is to substitute a logic level driven MOSFET for the 9 volt one.
     
  5. retched

    AAC Fanatic!

    Dec 5, 2009
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    I agree. You already have logic levels.. SO you might as well use a logic-level MOSFET.

    They are designed to be in full saturation at 5v at their rated operational current.
     
  6. beenthere

    Retired Moderator

    Apr 20, 2004
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    The OP specifically mentioned a JFET, which is why I asked for information. Power FET's take 10 volts to turn fully on (unless logic level).
     
  7. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    That point does need to be cleared up a bit.

    If the circuit designed is forced to use the JFET, a charge pump of sorts could be used to get the required voltage, but that seems a bit over-complicating things by assuming the JFET is in a switching application.
     
  8. dfro

    Thread Starter Active Member

    Feb 6, 2006
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    Thanks for the replies. I am sorry I was so vague in my question.

    I am interested in using a low resistance JFET as an audio switch. It can handle +25V from source to drain.

    The JFET is a depletion device, so I have to put a negative voltage on the gate compared to the source to turn it off. 0V between gate and source turns it all the way on.

    I would like to use a 9V power supply to make sure that the JFET does not clip a 2 to 4V peak-peak audio signal when turned on. I will add a couple diodes to the gate to add .6V*3=1.8V more headroom to the positive going signal.

    I would also like to make sure that the JFET does not unintentionally turn on because the audio signal dips too low causing the voltage between source and gate to be too small to keep it turned off.

    After a little research I found several examples, where a BJT and a high side or a low side load resistor is used to amplify a logic level signal so that logic LO or HI saturates the BJT all the way on or all the way off. In one text it was called a saturation amplifier. That is what I would like to use. But, that leaves me with another question.

    I would like to use a CMOS microcontroller to do the switching.
    How do I orient the MCU's power rails to the audio signal's Ground?

    I plan to connect +9V of the power supply to 0V of the audio signal. Ground of the power supply will then be -9V compared to audio signal ground.

    Can I tie the +5V power rail of the MCU to 0V of the audio signal?

    Oriented this way +5V of the MCU = 0V of the audio signal, and GND of the MCU = -5V of the audio signal. Through a BJT saturation amplifier, a logic HI would put the JFET gate at 0V audio signal, and logic LO would put the gate at -9V.

    Are there any problems with GND of the MCU not being at audio ground as far as noise or oscillation? Will the 100nF bypass caps between the MCU power rails be sufficient in this orientation?

    Another orientation would be to tie the MCU's ground to the power supply ground, which places it at -9V compared to the audio signal's Ground (0V).

    I hope I am making sense.

    Thanks,
    Dave
     
    Last edited: Jan 15, 2011
  9. thatoneguy

    AAC Fanatic!

    Feb 19, 2009
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    I'm still unsure of the question, it sounds like you are working with an audio signal, but you also mention switching.

    For very low current audio or switching, you can use a "Charge Pump" IC, which doubles voltage by charging capacitors in parallel and discharges them in series. Some will also change the polarity for a negative voltage, such as needed when using a dual supply op amp.

    If this is for audio, I would suggest a secondary switching supply that provided ±12V or whatever your need.

    For switching a MOSFET, the charge pump can be smaller and faster, since very little current is needed.
     
  10. dfro

    Thread Starter Active Member

    Feb 6, 2006
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    If I have a +/- 9V dual power supply, can I orient the MCU's power rails so that the Vcc pin is at 0V, and the GND pin is at -5V? Will this cause problems with noise, or will the 100nF bypass caps between the MCU's power pins be fine?

    Dave
     
  11. dfro

    Thread Starter Active Member

    Feb 6, 2006
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    I did a simulation with LTSpice of the switching circuit. It is switching successfully, but I have signal noise making it through the JFET when it is turned off. I have included a snapshot of the circuit.

    I have a 0V to -5V pulse coming out of V2, which simulates an MCU logic signal. V1 is the -9V power. V3 is simulating an audio signal with R2 as the source impedance. The 2N9207 amplifies the logic signal so that it swings from 0V to -9V. And, the zener and 1N4148 diode keep the JFET from clipping the signal on its positive voltage swing.

    With a 4Vp-p input signal, the noise making it through the JFET is about 4mVp-p. Is this signal leakage caused by the small capacitance between the Gate and Source? Or, is it coming from somewhere else?

    Is this leakage normal and at an acceptable level?

    Thanks,
    Dave
     
  12. dfro

    Thread Starter Active Member

    Feb 6, 2006
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    I think I found my answer.

    On a pair of JFET switch datasheets I just found, there are specs called "OFF isolation" and "Crosstalk". Both both specs are rated in decibels from 50 to 60 dB.

    My simulation is giving me an OFF isolation of:

    20log10(.004/4) =
    20log10(.001) =
    -60 db

    It looks like the JFET spice model is giving me a standard amount of signal leak.

    Correct?

    Dave
     
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