Hi everyone,

I made this circuit to lower the power usage of one of my early projects.

Idea was when the "SLEEP" wire receive a input from piazo element, the path to "GND" would open up (connected to the ground of my earlier project) and complete the circuit. "+V" common on both circuits (3.6V)

can anyone help me spot what I missed here, because it doesn't work for some reason

 

R6 is not providing a high impedance for the piezo, it is limiting base current. If the gain of T1 is normal, it will be saturated most of the time. If the piezo ever delivers a negative going voltage to shut off T1, emitter T2 will go high. When emitter T2 goes high, T3 would short out the negative power supply except C6 will destroy any short pulses from 2.

The LED will be on all the time and there is no latch in this circuit.

That's a start, but I have another person to talk to right now.

 

OK, I'm back. Either I am bad at figuring this out or you have several mistakes.
What's your plan, stage by stage?

 

OK, I'm back. Either I am bad at figuring this out or you have several mistakes.
What's your plan, stage by stage?

thanks for trying.

plan is to have to have the transistor just bias so the small input from the piezzo would short T3

 

To short T3, T2 has to be conducting. For T2 to be on, T1 has to be off. So you're hoping a negative going input will turn T1 off.

I'm afraid that a piezo is too feeble to do that. You have T1 biased on so much, and your input impedance so low, that the piezo can not overcome your input stage.

 

To short T3, T2 has to be conducting. For T2 to be on, T1 has to be off. So you're hoping a negative going input will turn T1 off.

I'm afraid that a piezo is too feeble to do that. You have T1 biased on so much, and your input impedance so low, that the piezo can not overcome your input stage.

any suggestions how I can tackle this. my projects takes up about 8mA at idle, I need to get that down to 0.5mA. this was the best I could come up with.

I only have the input from the pizzo to work with

 

My favorite high impedance amplifier circuit is a j-fet or a j-fet input op-amp. The J201 transistor works in the range of 200 ua to 1 ma.

CMOS op-amps are another high impedance, low current option. Probably better than a, "build it yourself" amplifier stage.

 

My favorite high impedance amplifier circuit is a j-fet or a j-fet input op-amp. The J201 transistor works in the range of 200 ua to 1 ma.

CMOS op-amps are another high impedance, low current option. Probably better than a, "build it yourself" amplifier stage.

having a look now. how would you suggest I incorporate one to the existing system?.

 

Start with , "Find an op-amp". You need a low voltage amp with low bias current.
http://www.mouser.com/Semiconductor...Z1yzmm0qZ1z0z63x&Ns=Ib - Input Bias Current|0

Use the first one to provide a high impedance input for the piezo and use the second one to make your logic function.