SWITCH in PIC18F4550

Discussion in 'Embedded Systems and Microcontrollers' started by 74266, Jul 20, 2016.

  1. 74266

    Thread Starter Member

    Mar 20, 2016
    41
    0
    Our professor wants us to make a program in MLab to show an output of the basic logic gates using pic18f where the inputs(switches) will be assign assign in RA1 and RA2

    RB0 = RA1 + RA2
    RB3 = RA1 * RA2
    RB4 =RA1 xor RA2
    RB7 =RA1 xnor RA2
    also he don't want us to use bit oriented operation so we must use byte oriented operation only and no using of C programming
     
  2. R!f@@

    AAC Fanatic!

    Apr 2, 2009
    8,754
    760
    Wow ! how to you use a PIC without programming.
     
  3. 74266

    Thread Starter Member

    Mar 20, 2016
    41
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    Like this
    Code (Microchip Assembler):
    1.  
    2. #include "P18F4550.inc"
    3.  
    4. config  FOSC = HS        
    5. config  CPUDIV = OSC1_PLL2
    6. config  PLLDIV = 1  
    7. config  PWRT = OFF  
    8. config  BOR = OFF  
    9. config  WDT = OFF  
    10. config  MCLRE = ON  
    11. config  STVREN = ON  
    12. config  LVP = OFF
    13. config  ICPRT = OFF  
    14. config  XINST = OFF  
    15. config  DEBUG = OFF  
    16. config  FCMEN = OFF
    17. config  IESO = OFF
    18. config  LPT1OSC = OFF
    19. config  CCP2MX = ON  
    20. config  PBADEN = OFF
    21. config  USBDIV = 2
    22. config  VREGEN = OFF
    23.  
    24. R1    equ 0x000  
    25. R2    equ 0x001
    26.  
    27.  
    28. org 0x0000
    29.  
    30. BRA START
    31.  
    32. org 0x0008
    33. RETFIE FAST
    34.  
    35. org 0x0018
    36. RETFIE
    37.  
    38. START
    39. ; Initialization
    40. ; Disable analog comparators multiplexed on RA and RB
    41. MOVLW 0x0F
    42. MOVWF ADCON1, ACCESS
    43. MOVLW 0x07
    44. MOVWF CMCON, ACCESS
    45.  
    46. ; Initialize RA[1-2] as input: the rest as output  
    47. ; Initialize RB[0-7] as output
    48. ; Initialize RD[0-7] as output
    49. MOVLW 0x06
    50. MOVWF TRISA, ACCESS
    51. CLRF TRISB, ACCESS
    52. CLRF TRISD, ACCESS
    53.  
    54.  
    55. LOOP
    56.  
    57. ;SEQUENCE 0
    58. MOVF PORTA,W,ACCESS;0000 0000/0000 0010
    59. MOVWF LATB,ACCESS
    60.  
    61. ; Sequence 1
    62. ; Read current logic levels of pins of RA then store to memory location R1
    63. MOVF PORTA, W, ACCESS
    64.     ;0000 0010
    65. MOVWF R1, ACCESS
    66.  
    67. ;0000 0010
    68. ; Complement the current value of R1
    69. COMF R1, F, ACCESS
    70.     ;1111 1101
    71.  
    72. ; Shift to the right
    73. RRNCF R1, F, ACCESS
    74.    ;1111 1110
    75.  
    76. ; Cancel out all other bits except bit 0
    77. MOVLW 0x01
    78.              ;0000 0001
    79. ANDWF R1, F, ACCESS
    80.    ;0000 0000
    81.  
    82. ; Send the current value of R1 to LATA
    83. MOVF R1, W, ACCESS
    84.     ;0000 0000
    85. MOVWF LATA, ACCESS
    86.  
    87. MOVF PORTA,W,ACCESS
    88. MOVWF R1,ACCESS ; 0000 0000 / 0000 0010
    89. COMF R1,F,ACCESS ;1111 1111 / 1111 1101
    90. RLNCF R1,F,ACCESS;
    91. RLNCF R1,F,ACCESS;
    92. RLNCF R1,F,ACCESS;
    93. RLNCF R1,F,ACCESS;1111 1111 / 1101 1111
    94. MOVLW 0X20;        0010 0000
    95. ANDWF R1,F,ACCESS;0010 0000 / 0000 0000
    96. MOVF R1,W,ACCESS; 0100 0000 / 0000 0000
    97. MOVWF LATB,ACCESS;0100 0000 / 0000 0000
    98.  
    99. ; Sequence 2
    100. ; Read current logic levels of pins of RA then store to memory location R1
    101.  
    102. MOVF PORTA, W, ACCESS
    103. MOVWF R1, ACCESS
    104.  
    105. ;0000 0000    / 0000 0100
    106.  
    107. ; Complement the current value of R1
    108. COMF R1, F, ACCESS
    109.   ;1111 1111  
    110. /1111 1011  
    111. ; Shift to the right five times (5x)
    112.  
    113. RLNCF R1, F, ACCESS
    114.    ;1111 1111 /1111 0111
    115. RLNCF R1, F, ACCESS
    116.    ;1111 1111 /1110 1111
    117. RLNCF R1, F, ACCESS
    118.    ;1111 1111 /1101 1111
    119. RLNCF R1, F, ACCESS
    120.    ;1111 1111 /1011 1111
    121. RLNCF R1, F, ACCESS
    122.    ;1111 1111
    123. /0111 1111  
    124. ; Cancel out all other bits except bit 7
    125. MOVLW 0x80
    126.  
    127. ANDWF R1, F, ACCESS
    128.  
    129. ;1000 0000    /0000 0000
    130.  
    131. ; Send the current value of R1 to LATD
    132. MOVF R1, W, ACCESS
    133.  
    134. MOVWF LATD, ACCESS
    135.  
    136. MOVF PORTA,W,ACCESS
    137. MOVWF R1,ACCESS ;0000 0100 / 0000 0000
    138. COMF R1,F,ACCESS;1111 1011 / 1111 1111
    139. RRNCF R1,F,ACCESS;
    140. RRNCF R1,F,ACCESS;
    141. RRNCF R1,F,ACCESS;
    142. RRNCF R1,F,ACCESS;1011 1111 / 1111 1111
    143. MOVLW 0X40;0100 0000
    144. ANDWF R1,F,ACCESS;0000 0000 / 0100 0000
    145. MOVF R1,W,ACCESS
    146. MOVWF LATB,ACCESS;0000 0000 /0100 0000
    147.  
    148. ; Repeat the sequence  
    149. BRA LOOP
    150. end
    Mod edit: please use code tags for posting code
     
    Last edited by a moderator: Jul 21, 2016
  4. dannyf

    Well-Known Member

    Sep 13, 2015
    1,809
    362
    Code it in C, then submit the compiler generated disassembly file.

    Done.
     
  5. NorthGuy

    Active Member

    Jun 28, 2014
    604
    121
    Probably he meant something of that sort

    Code (Microchip Assembler):
    1.   rrncf PORTA,w ; load data bits x-x-x-x-x-x-A2-A1
    2.   andlw 0x03   ; remove unneeded bits 0-0-0-0-0-0-A2-A1
    3.   addlw 0x7d   ; calculate the required entities and simultaneously separate (A1*A2) from (A1+A2)
    4.                ; result: (A1*A2)-x-x-x-x-x-(A1+A2)-0
    5.   rrncf WREG,w ; shift it to the very right x-(A1*A2)-x-x-x-x-x-(A1+A2)
    6.   andlw 0x41   ; clean-up 0-(A1*A2)-0-0-0-0-0-(A1+A2)
    7.   addlw 0x4f   ; shift (A1*A2) and (A1+A2) into the places and simultaneously
    8.                ; calculate nxor - (A1*A2)-x-0-(A1+A2)-x-x-x-(A1 nxor A2)
    9.   andlw 0x91   ; clean-up (A1*A2)-0-0-(A1+A2)-0-0-0-(A1 nxor A2)
    10.   addlw 0x07   ; shift (A1 nxor A2) into the place and simultaneously calculate
    11.                ; xor - (A1*A2)-0-0-(A1+A2)-(A1 nxor A2)-x-x-(A1 xor A2)
    12.   swapf WREG,w ; now everything is as requested (A1 nxor A2)-x-x-(A1 xor A2)-(A1*A2)-0-0-(A1+A2)
    13.   xorwf LATB,w ; to avoid disturbing unused bits in port B do a XOR swap
    14.   andlw 0x99
    15.   xorwf LATB,f ; done
    edit: fixed a bug. First line - needs to read PORTA, not LATA.
     
    Last edited: Jul 21, 2016
  6. 74266

    Thread Starter Member

    Mar 20, 2016
    41
    0
    NorthGuy

    I can't imagine the output since I don't know the value of LATB before the operation xorwf LATB,w. Can you please show the output if RA1 =1 and RA2 =1

    Code (Microchip Assembler):
    1.  
    2. rrncf LATA,w ; load data bits x-x-x-x-x-x-A2-A1                         w =    0000 0011
    3.   andlw 0x03   ; remove unneeded bits 0-0-0-0-0-0-A2-A1                        w =    0000 0011
    4.   addlw 0x7d   ; calculate the required entities and simultaneously separate (A1*A2) from (A1+A2)w =    0111 1101 ->0000 0001
    5.                ; result: (A1*A2)-x-x-x-x-x-(A1+A2)-0
    6.   rrncf WREG,w ; shift it to the very right x-(A1*A2)-x-x-x-x-x-(A1+A2)                w =    1000 0000
    7.   andlw 0x41   ; clean-up 0-(A1*A2)-0-0-0-0-0-(A1+A2)                        w =    1000 0000 & 0100 0001 = 0000 0000
    8.   addlw 0x4f   ; shift (A1*A2) and (A1+A2) into the places and simultaneously            w =    0000 0000 & 0100 1111 = 0000 0000
    9.                ; calculate nxor - (A1*A2)-x-0-(A1+A2)-x-x-x-(A1 nxor A2)            w =  
    10.   andlw 0x91   ; clean-up (A1*A2)-0-0-(A1+A2)-0-0-0-(A1 nxor A2)                w =     0000 0000 & 1001 0001 = 0000 0000
    11.   addlw 0x07   ; shift (A1 nxor A2) into the place and simultaneously calculate            w =    0000 0000 & 0000 0111 = 0000 0000
    12.                ; xor - (A1*A2)-0-0-(A1+A2)-(A1 nxor A2)-x-x-(A1 xor A2)
    13.   swapf WREG,w ; now everything is as requested (A1 nxor A2)-x-x-(A1 xor A2)-(A1*A2)-0-0-(A1+A2) w =     0000 0000
    14.   xorwf LATB,w ; to avoid disturbing unused bits in port B do a XOR swap            w =  
    15.   andlw 0x99
    16.   xorwf LATB,f ; done
     
    Last edited by a moderator: Jul 21, 2016
  7. JohnInTX

    Moderator

    Jun 26, 2012
    2,345
    1,028
    That is terrible advice.
     
  8. NorthGuy

    Active Member

    Jun 28, 2014
    604
    121
    You made a number of mistakes following the results of the operation. Here how it goes:

    Code (Microchip Assembler):
    1.   rrncf PORTA,w;  w =    xxxx xx11
    2.   andlw 0x03   ;  w =    0000 0011
    3.   addlw 0x7d   ;  w =    1000 0000
    4.   rrncf WREG,w ;  w =    0100 0000
    5.   andlw 0x41   ;  w =    0100 0000
    6.   addlw 0x4f   ;  w =    1000 1111
    7.   andlw 0x91   ;  w =    1000 0001
    8.   addlw 0x07   ;  w =    1000 1000
    9.   swapf WREG,w ;  w =    1000 1000
    At this point the result is in WREG. You may clean it and write to LATB:

    Code (Microchip Assembler):
    1.   andlw 0x99 ;  w =   1000 1000
    2.   movwf LATB ; latb = 1000 1000
    However, this would clear RB1,RB2,RB5 and RB6. To preserve the values which are there, you do the XOR swap (google it) instead. Say, if LATB was all ones (1111 1111)

    Code (Microchip Assembler):
    1.   xorwf LATB,w ;  w =   0111 0111
    2.   andlw 0x99   ; w =    0001 0001
    3.   xorwf LATB,f ; latb = 1110 1110
    Both version of the ending do the same thing with RB0,RB3,RB4, and RB7 - these get moved from W to LATB. But the first code sets the rest of the bits to 0, while the second one preserves whatever was in these bits before.
     
    74266 and JohnInTX like this.
  9. atferrari

    AAC Fanatic!

    Jan 6, 2004
    2,648
    763
    Much better than looking at the disassembly is simulating every operation separately with MPSIM and then look at the outcome in the watch window.

    If you are organized, you could do it in minutes and learn a lot. Otherwise, your classmate :p from the North is going to take all credits.
     
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  10. 74266

    Thread Starter Member

    Mar 20, 2016
    41
    0
    Thank you very much for correction and clarification
    but if the value I use for RA1 =1 and RA2 =1
    Doesn't the value when it was send to LATB become this
    RB0 =(1)
    RB1 =0
    RB2 =0
    RB3 =(1)
    RB4 =(0)
    RB5 =0
    RB6 =0
    RB7 =(1)
     
  11. NorthGuy

    Active Member

    Jun 28, 2014
    604
    121
    No, It becomes 0x88 (10001000). See my previous post for step-by-step values.

    Why do you think it has 1 in RB0?
     
  12. 74266

    Thread Starter Member

    Mar 20, 2016
    41
    0
    Because in Basic Logic OR
    In Truth Table
    RA1 RA2 RB0
    0 0 0
    0 1 1
    1 0 1
    1 1 1
     
    Last edited: Jul 22, 2016
  13. NorthGuy

    Active Member

    Jun 28, 2014
    604
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    The assignment says "+" not "or". May be the same if you're taking formal logic classes, but totally different things if you do programming. To see the difference, try these in C:

    Code (C):
    1. RB0 = RA1 + RA2;
    2. RB0 = RA1 | RA2;
    3. RB0 = RA1 || RA2;
    But, you now know how to do such things, so if "or" is what you want you can modify it to do "or".
     
  14. dannyf

    Well-Known Member

    Sep 13, 2015
    1,809
    362
    Here is a C-translated XOR() and AND() operations:

    Code (Text):
    1.  
    2. 35:                       //xor gate
    3. 36:                       if (XOR(XORIN1, XORIN2)) IO_SET(XOROUT_PORT, XOROUT);
    4.    7E5    3000     MOVLW 0
    5.    7E6    1283     BCF 0x3, 0x5
    6.    7E7    1886     BTFSC 0x6, 0x1
    7.    7E8    3001     MOVLW 0x1
    8.    7E9    00F0     MOVWF 0x70
    9.    7EA    3000     MOVLW 0
    10.    7EB    01F1     CLRF 0x71
    11.    7EC    1806     BTFSC 0x6, 0
    12.    7ED    3001     MOVLW 0x1
    13.    7EE    00F2     MOVWF 0x72
    14.    7EF    01F3     CLRF 0x73
    15.    7F0    0670     XORWF 0x70, W
    16.    7F1    00F4     MOVWF 0x74
    17.    7F2    0871     MOVF 0x71, W
    18.    7F3    0673     XORWF 0x73, W
    19.    7F4    00F5     MOVWF 0x75
    20.    7F5    0474     IORWF 0x74, W
    21.    7F6    1903     BTFSC 0x3, 0x2
    22.    7F7    2FFA     GOTO 0x7fa
    23.    7F8    1506     BSF 0x6, 0x2
    24.    7F9    2FFB     GOTO 0x7fb
    25. 37:                       else IO_CLR(XOROUT_PORT, XOROUT);
    26.    7FA    1106     BCF 0x6, 0x2
    27. 38:                      
    28. 39:                       //and gate
    29. 40:                       if (AND(ANDIN1, ANDIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
    30.    7FB    1986     BTFSC 0x6, 0x3
    31.    7FC    1E06     BTFSS 0x6, 0x4
    32.    7FD    2FE4     GOTO 0x7e4
    33.    7FE    1686     BSF 0x6, 0x5
    34.    7FF    2FE5     GOTO 0x7e5
    35. 41:                       else IO_CLR(ANDOUT_PORT, ANDOUT);
    36.  
    Obviously, for a specific set of input / output configuration.

    All done in a few seconds.
     
  15. NorthGuy

    Active Member

    Jun 28, 2014
    604
    121
    First, it used bit operations which are forbidden by the assignment, so the best it can get is probably C-.

    Then, if a machine does your assignments for you, don't you think that the machine should get the degree, not you :)
     
  16. dannyf

    Well-Known Member

    Sep 13, 2015
    1,809
    362
    here is the complete implementation of all the four gates, on the same pins the assignment asked for:

    Code (Text):
    1.  
    2. 54:                       //or gate
    3. 55:                       if (OR(ORIN1, ORIN2)) IO_SET(OROUT_PORT, OROUT);
    4.    7D0    1885     BTFSC 0x5, 0x1
    5.    7D1    2FD4     GOTO 0x7d4
    6.    7D2    1D05     BTFSS 0x5, 0x2
    7.    7D3    2FD6     GOTO 0x7d6
    8.    7D4    1406     BSF 0x6, 0
    9.    7D5    2FD7     GOTO 0x7d7
    10. 56:                       else IO_CLR(OROUT_PORT, OROUT);
    11.    7D6    1006     BCF 0x6, 0
    12. 57:              
    13. 58:                       //and gate
    14. 59:                       if (AND(ANDIN1, ANDIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
    15.    7D7    1885     BTFSC 0x5, 0x1
    16.    7D8    1D05     BTFSS 0x5, 0x2
    17.    7D9    2FDC     GOTO 0x7dc
    18.    7DA    1586     BSF 0x6, 0x3
    19.    7DB    2FDD     GOTO 0x7dd
    20. 60:                       else IO_CLR(ANDOUT_PORT, ANDOUT);
    21.    7DC    1186     BCF 0x6, 0x3
    22. 61:              
    23. 62:                       //xor gate
    24. 63:                       if (XOR(XORIN1, XORIN2)) IO_SET(XOROUT_PORT, XOROUT);
    25.    7DD    1D05     BTFSS 0x5, 0x2
    26.    7DE    2FE1     GOTO 0x7e1
    27.    7DF    3001     MOVLW 0x1
    28.    7E0    2FE2     GOTO 0x7e2
    29.    7E1    3000     MOVLW 0
    30.    7E2    00F0     MOVWF 0x70
    31.    7E3    1C85     BTFSS 0x5, 0x1
    32.    7E4    2FE7     GOTO 0x7e7
    33.    7E5    3001     MOVLW 0x1
    34.    7E6    2FE8     GOTO 0x7e8
    35.    7E7    3000     MOVLW 0
    36.    7E8    0670     XORWF 0x70, W
    37.    7E9    1903     BTFSC 0x3, 0x2
    38.    7EA    2FED     GOTO 0x7ed
    39.    7EB    1606     BSF 0x6, 0x4
    40.    7EC    2FEE     GOTO 0x7ee
    41. 64:                       else IO_CLR(XOROUT_PORT, XOROUT);
    42.    7ED    1206     BCF 0x6, 0x4
    43. 65:              
    44. 66:                       //xNor gate
    45. 67:                       if (XNOR(XNORIN1, XNORIN2)) IO_SET(XNOROUT_PORT, XNOROUT);
    46.    7EE    1D05     BTFSS 0x5, 0x2
    47.    7EF    2FF2     GOTO 0x7f2
    48.    7F0    3001     MOVLW 0x1
    49.    7F1    2FF3     GOTO 0x7f3
    50.    7F2    3000     MOVLW 0
    51.    7F3    00F0     MOVWF 0x70
    52.    7F4    1C85     BTFSS 0x5, 0x1
    53.    7F5    2FF8     GOTO 0x7f8
    54.    7F6    3001     MOVLW 0x1
    55.    7F7    2FF9     GOTO 0x7f9
    56.    7F8    3000     MOVLW 0
    57.    7F9    0670     XORWF 0x70, W
    58.    7FA    1D03     BTFSS 0x3, 0x2
    59.    7FB    2FFE     GOTO 0x7fe
    60.    7FC    1786     BSF 0x6, 0x7
    61.    7FD    2FD0     GOTO 0x7d0
    62. 68:                       else IO_CLR(XNOROUT_PORT, XNOROUT);
    63.    7FE    1386     BCF 0x6, 0x7
    64.    7FF    2FD0     GOTO 0x7d0
    65.  
    66.  
    All comes to about 50 bytes.

    the chip i implemented this on is a 16F690 so you can disassemble the addresses into macros in order to make it more human-readable. The code actually runs correctly as is.
     
  17. dannyf

    Well-Known Member

    Sep 13, 2015
    1,809
    362
    The code I posted earlier provides the most flexibility: each logic function can have its own and different inputs -> in this case, they are configured to the same.

    Its downside is that it doesn't maintain atomiocity.

    The following implementation maintains atomicity: all logic functions are tested on the same states of the pins so their output is logically consistent at all times.

    Code (Text):
    1.  
    2.                       lvar = IO_GET(LIN_PORT, LIN1 | LIN2);    //read the logic input
    3.    7CD    1283     BCF 0x3, 0x5
    4.    7CE    0805     MOVF 0x5, W
    5.    7CF    00F0     MOVWF 0x70
    6.    7D0    3006     MOVLW 0x6
    7.    7D1    05F0     ANDWF 0x70, F
    8. 49:                      
    9. 50:                       //or gate
    10. 51:                       if (OR(LIN1, LIN2)) IO_SET(OROUT_PORT, OROUT);
    11.    7D2    18F0     BTFSC 0x70, 0x1
    12.    7D3    2FD6     GOTO 0x7d6
    13.    7D4    1D70     BTFSS 0x70, 0x2
    14.    7D5    2FD8     GOTO 0x7d8
    15.    7D6    1407     BSF 0x7, 0
    16.    7D7    2FD9     GOTO 0x7d9
    17. 52:                       else IO_CLR(OROUT_PORT, OROUT);
    18.    7D8    1007     BCF 0x7, 0
    19. 53:                
    20. 54:                       //and gate
    21. 55:                       if (AND(LIN1, LIN2)) IO_SET(ANDOUT_PORT, ANDOUT);
    22.    7D9    18F0     BTFSC 0x70, 0x1
    23.    7DA    1D70     BTFSS 0x70, 0x2
    24.    7DB    2FDE     GOTO 0x7de
    25.    7DC    1587     BSF 0x7, 0x3
    26.    7DD    2FDF     GOTO 0x7df
    27. 56:                       else IO_CLR(ANDOUT_PORT, ANDOUT);
    28.    7DE    1187     BCF 0x7, 0x3
    29. 57:                
    30. 58:                       //xor gate
    31. 59:                       if (XOR(LIN1, LIN2)) IO_SET(XOROUT_PORT, XOROUT);
    32.    7DF    1D70     BTFSS 0x70, 0x2
    33.    7E0    2FE3     GOTO 0x7e3
    34.    7E1    3001     MOVLW 0x1
    35.    7E2    2FE4     GOTO 0x7e4
    36.    7E3    3000     MOVLW 0
    37.    7E4    00F1     MOVWF 0x71
    38.    7E5    1CF0     BTFSS 0x70, 0x1
    39.    7E6    2FE9     GOTO 0x7e9
    40.    7E7    3001     MOVLW 0x1
    41.    7E8    2FEA     GOTO 0x7ea
    42.    7E9    3000     MOVLW 0
    43.    7EA    0671     XORWF 0x71, W
    44.    7EB    1903     BTFSC 0x3, 0x2
    45.    7EC    2FEF     GOTO 0x7ef
    46.    7ED    1607     BSF 0x7, 0x4
    47.    7EE    2FF0     GOTO 0x7f0
    48. 60:                       else IO_CLR(XOROUT_PORT, XOROUT);
    49.    7EF    1207     BCF 0x7, 0x4
    50. 61:                
    51. 62:                       //xNor gate
    52. 63:                       if (XNOR(LIN1, LIN2)) IO_SET(XNOROUT_PORT, XNOROUT);
    53.    7F0    1D70     BTFSS 0x70, 0x2
    54.    7F1    2FF4     GOTO 0x7f4
    55.    7F2    3001     MOVLW 0x1
    56.    7F3    2FF5     GOTO 0x7f5
    57.    7F4    3000     MOVLW 0
    58.    7F5    00F1     MOVWF 0x71
    59.    7F6    1CF0     BTFSS 0x70, 0x1
    60.    7F7    2FFA     GOTO 0x7fa
    61.    7F8    3001     MOVLW 0x1
    62.    7F9    2FFB     GOTO 0x7fb
    63.    7FA    3000     MOVLW 0
    64.    7FB    0671     XORWF 0x71, W
    65.    7FC    1D03     BTFSS 0x3, 0x2
    66.    7FD    2FCC     GOTO 0x7cc
    67.    7FE    1787     BSF 0x7, 0x7
    68.    7FF    2FCD     GOTO 0x7cd
    69. 64:                       else IO_CLR(XNOROUT_PORT, XNOROUT);
    70. 65:                      
    71.  
    72.  
    73.  
    The output port is PORTC. Pin assignment is the same.
     
  18. NorthGuy

    Active Member

    Jun 28, 2014
    604
    121
    Is it just me, or you're building your own assembler-like commands on top of the C?
     
  19. dannyf

    Well-Known Member

    Sep 13, 2015
    1,809
    362
    Does it work? Check, :)

    Using the code posted earlier.
     
  20. 74266

    Thread Starter Member

    Mar 20, 2016
    41
    0
    I forgot to post this but this is the output my professor made


    Code (Text):
    1.  
    2.                
    3.    #include "P18F4550.inc"
    4.    
    5.     config  FOSC = HS      
    6.     config  CPUDIV = OSC1_PLL2
    7.     config  PLLDIV = 1
    8.     config  PWRT = OFF
    9.     config  BOR = OFF
    10.     config  WDT = OFF
    11.     config  MCLRE = ON
    12.     config  STVREN = ON
    13.     config  LVP = OFF
    14.     config  ICPRT = OFF
    15.     config  XINST = OFF
    16.     config  DEBUG = OFF
    17.     config  FCMEN = OFF
    18.     config  IESO = OFF
    19.     config  LPT1OSC = OFF
    20.     config  CCP2MX = ON
    21.     config  PBADEN = OFF
    22.     config  USBDIV = 2
    23.     config  VREGEN = OFF
    24.    
    25.     INPUT   equ 0x000    ; BANK 0
    26.     OUTPUT  equ 0x100    ; BANK 1
    27.     TEMP    equ 0X001    ; BANK 0
    28.    
    29.     org 0x0000
    30.     BRA START
    31.    
    32.     org 0x0008
    33.     RETFIE FAST
    34.    
    35.     org 0x0018
    36.     RETFIE
    37.    
    38. START
    39.     ; Disable Analog Comparators multiplexed with RA & RB
    40.     MOVLW 0x0F
    41.     MOVWF ADCON1, ACCESS
    42.     MOVLW 0x07
    43.     MOVWF CMCON, ACCESS
    44.    
    45.     ; Set the direction of RA[1-2] to INPUT; Rest is OUTPUT
    46.     MOVLW 0x06
    47.     MOVWF TRISA, ACCESS
    48.    
    49.     ; Set the direction of RB[0-7] to OUTPUT
    50.     CLRF TRISB, ACCESS
    51. LOOP
    52.     ; Init OUTPUT = 0x00
    53.     MOVLB 0x1
    54.     CLRF OUTPUT, BANKED
    55.    
    56.     ; RB[0] = RA[1] OR RA[2]
    57.     ; RB[1] = RA[1]
    58.     ; RB[2] = RA[2]
    59.     ; RB[3] = RA[1] AND RA[2]
    60.     ; RB[4] = RA[1] XOR RA[2]
    61.     ; RB[5] = NOT RA[1]
    62.     ; RB[6] = NOT RA[2]
    63.     ; RB[7] = RA[1] XNOR RA[2]
    64.     ; MOVWF LATB, ACCESS ONCE
    65.    
    66.     ; Read the cuurent logic of the switches
    67.     MOVF PORTA, W, ACCESS
    68.     MOVWF INPUT, ACCESS
    69.    
    70.     ; RB[1|2] = RA[1|2]
    71.     ANDLW 0x06
    72.     MOVLB 0x1
    73.     MOVWF OUTPUT, BANKED
    74.    
    75.     ; RB[5|6] = NOT RA[1|2]
    76.     MOVF INPUT, W, ACCESS
    77.     MOVWF TEMP, ACCESS
    78.     COMF TEMP, F, ACCESS
    79.     SWAPF TEMP, W, ACCESS
    80.     ANDLW 0x60
    81.     MOVLB 0x1
    82.     IORWF OUTPUT, F, BANKED
    83.    
    84.     ; RB[0] = RA[1] OR RA[2]
    85.     MOVF INPUT, W, ACCESS   ; R1
    86.     MOVWF TEMP, ACCESS       ; R2
    87.     RRNCF TEMP, F, ACCESS   ; BIT 1
    88.     IORWF TEMP, F, ACCESS
    89.     RRNCF TEMP, W, ACCESS
    90.     ANDLW 0x01
    91.     MOVLB 0x1
    92.     IORWF OUTPUT, F, BANKED
    93.    
    94.     ; RB[3] = RA[1] AND RA[2]
    95.     MOVF INPUT, W, ACCESS   ; R1
    96.     MOVWF TEMP, ACCESS       ; R2
    97.     RLNCF TEMP, F, ACCESS   ; BIT 2
    98.     ANDWF TEMP, F, ACCESS
    99.     RLNCF TEMP, W, ACCESS
    100.     ANDLW 0x08
    101.     MOVLB 0x1
    102.     IORWF OUTPUT, F, BANKED
    103.    
    104.     ; RB[4] = RA[1] XOR RA[2]
    105.     MOVF INPUT, W, ACCESS   ; R1
    106.     MOVWF TEMP, ACCESS       ; R2
    107.     RRNCF TEMP, F, ACCESS   ; BIT 1
    108.     XORWF TEMP, F, ACCESS  
    109.     RRNCF TEMP, F, ACCESS
    110.     SWAPF TEMP, W, ACCESS
    111.     ANDLW 0x10
    112.     MOVLB 0x1
    113.     IORWF OUTPUT, F, BANKED
    114.    
    115.     ; RB[7] = RA[1] XNOR RA[2]
    116.     MOVF INPUT, W, ACCESS   ; R1
    117.     MOVWF TEMP, ACCESS       ; R2
    118.     RLNCF TEMP, F, ACCESS   ; BIT 2
    119.     XORWF TEMP, F, ACCESS
    120.     COMF TEMP, F, ACCESS    ; XNOR
    121.     RLNCF TEMP, F, ACCESS
    122.     SWAPF TEMP, W, ACCESS
    123.     ANDLW 0x80
    124.     MOVLB 0x1
    125.     IORWF OUTPUT, W, BANKED
    126.    
    127.     MOVWF LATB, ACCESS
    128.    
    129.     BRA LOOP
    130.    
    131.     end
    132.    
    133.  
    134.  
     
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