Successive Approximation ADC

Discussion in 'Homework Help' started by Durzo972, Nov 16, 2012.

  1. Durzo972

    Thread Starter New Member

    Nov 16, 2012

    I have a midterm coming up and just wanting to confirm if these answers make sense

    The Maxim MAX11100 16-bit successive approximation ADC is rated for a maximum clock frequency of 4.8MHz and requires 8 clock cycles for sample and hold acquisition time.

    a. What is the minimum conversion time for the ADC?

    Is the conversion time just (1/4.8 MHz)* 8 = 1.67 us?

    b. We wish to sample a signal with a maximum frequency component of 90 kHz. Could we successfully sample the signal without aliasing using the MAX11100? Be sure to justify your answer.

    Now what im not too sure if i should consider the maximum clock frequency as the sampling frequency? therefore the ADC should easily sample the signal without aliasing since the nyquist theorem just states that the sampling frequency should be at least twice as much as the input's maximum frequency component

    Thanks for the input.
  2. crutschow


    Mar 14, 2008
    The sample frequency is the inverse of the conversion time.
  3. tshuck

    Well-Known Member

    Oct 18, 2012
    Minimum sample frequency for a 90kHz signal is 180kHz, or double the highest frequency component of the sampled signal, as given by the Nyquist Sampling Theorem.

    This means that the maximum frequency of a signal that the ADC can sample and still reconstruct is 1/2 the maximum sample rate of the ADC.
  4. MrChips


    Oct 2, 2009
    It would take 16 clock cycles to perform a 16-bit successive approximation.
    Add 8 clock cycles for sample and hold. That gives 24 clock cycles to perform a conversion.
  5. WBahn


    Mar 31, 2012
    Strictly speaking, I don't think that the answer can really be known without consulting the data sheet. For instance, is the input buffered so that the next sample is being acquired while the present same it being converted and the last same is being exported. Or is this a brain dead part that has no pipelining at all. The data sheet shows it to be brain dead (which is not a bad thing, provided it is correspondingly cheap).

    The data sheet says 200kSa/s conversion rate, matching McChip's conclusion -- and also being the best answer you can make without knowing anything more about the part. But you should write down your assumptions.
  6. Durzo972

    Thread Starter New Member

    Nov 16, 2012
    First of all thank you for everyone's help and i just want to confirm a few things as well. So the 200kSa/s is the maximum sampling frequency(from what i understand crutschow is trying to say) therefore it can definately sample the signal without aliasing? I am having a hard time understanding why we add the 8 clock cycles for the sample and hold. Thanks
  7. WBahn


    Mar 31, 2012
    Provided the input signal is appropriately filtered (i.e., has an antialiasing filter on it so that the noise doesn't get aliased, either), you should be okay.

    Before the conversion even starts, the sample and hold circuitry has to settle. IIRC, they actually start converting after six clocks, but the first bit of data doesn't come out for another two clock cycles (since decisions have to be made before the value of those bits start to be known). It this requires 16 clocks in order to complete the conversion and export the result.

    Not all successive approximation converters do it this way, which is why you really need to refer to the data sheet for the part in question for the answer.