# Submission: Another Look at Synchronous Counters

Discussion in 'Feedback and Suggestions' started by tshuck, Mar 7, 2013.

## So, what did you think?

100.0%

0 vote(s)
0.0%
1. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
This section is intended to supplement the section already present on synchronous counters and immediately follow it. This is meant to formalize the process of sequential logic design as applies to counters, using many techniques used in subsequent sections, namely modulus counters(which I will post for review shortly), and finite state machines.

Again, let me know if anything is wrong or if you think it can be improved(and I will debate you).

Thanks for taking the time to give it a read through!

Last edited: Mar 7, 2013
2. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
Another Look at Synchronous Counters

So far, we have seen counters designed by inspection: determining what steps would produce a specific count sequence by means of examining the count sequence and inferring a relationship between each count step. Allow us now to formalize this procedure.

Take a counter that counts from 0 to 15. This counter contains 4 flip flops and counts as the following count sequence shows:

This count is representative of the output states of the flip flops, or what is called the current state.

Allow us to put another column into the table, this column corresponds to the next state, or the state of the output for each individual flip flop output after the current state is finished. All we have done is defined where the count will go after the current state is finished. As the next state is dependent upon the current state, the next state is dependent on the current state's flip flop output state, representing the current state. One way to look at it is, identify a row in the table, imagine the current state column is where the count currently is, and the next state column is where it will go on the next clock-edge.

This table is called a state table: it describes the current state of the device and the next state, which, depending on application, is not always a sequential count.

In order to make each state progress to the next state in our state table, we need to implement the Boolean function represented by the state transitions. This is called our input-forming logic as it forms the input to our flip flops and dictates the state transitions.

Next, we need to determine the truth table for each flip flop. We can see that the truth table for any individual flip flop is simply the column for the corresponding flip flop in the state table.

Following this logic for the following flip flops, we shall create Karnaugh maps to minimize each function's implementation using JK flip flops.

From the results, each input for each flip flop is simply a Boolean function, which we will implement using gates in our circuit, connecting our flip flop inputs as the Karnaugh maps describe.

Last edited: Jan 21, 2014
3. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
Connecting the circuit as prescribed by the minimized input-forming logic, we get the following circuit.

This circuit will operate as a counter, counting from 0 to 15, and then wrapping around to 0 after the count is finished. Upon rearranging this circuit's layout, we arrive at a familiar image:

Indeed, this is the design we came up with for our synchronous counter from the previous section! This approach can be used to determine any arbitrary counter and extends beyond this as more advanced circuits are processed.

File size:
1.4 KB
Views:
480
File size:
3.6 KB
Views:
496
File size:
4.8 KB
Views:
515
File size:
74.8 KB
Views:
525
File size:
38.3 KB
Views:
520
• ###### Another Look at Synchronous Counters.zip
File size:
463.8 KB
Views:
34
Last edited: Jan 31, 2014
4. ### Wendy Moderator

Mar 24, 2008
20,772
2,540
I am running at half speed at the moment, tagged for overtime again (they really, really love me). I am impressed with what I've seen so far. My skills in this area are a bit rusty, I've done it so long my way it is automatic, I don't even think in terms of process.

I'll give it a fine read Sunday/Monday though.

Remember, if you need to add a section between #1 and #2 just ask, we can do that now.

5. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
...both a blessing and a curse!

Don't push yourself to read this, it'll be floating about for a while
I think that is the problem with most books, to those that do it for years(authors), the answer seems obvious, but a new person needs to be introduced to the process before that, "A-Ha!" moment.

No pressure!

Thanks, but this was a short one and that's all there is to it. The next one ,that I'm probably going to post tonight, will be multiple posts again, so I may just take you up on that!

6. ### Georacer Moderator

Nov 25, 2009
5,151
1,266
That was actually very good! Nothing short of textbook level material. Well done!

I 'm surprised that it came out so short. Before reading it I expected more, but I don't think there's anything left out.

I would add, to emphasize, that the next state for each FF is a function of all of the previous four FF states.

tshuck likes this.
7. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
Excellent point! I will add that...

8. ### tshuck Thread Starter Well-Known Member

Oct 18, 2012
3,531
675
I was debating whether or not to bump this, but I am updating the entry and adding another image, so I think it is justified.

File size:
50.4 KB
Views:
451
9. ### MrChips Moderator

Oct 2, 2009
12,625
3,451
I wish to add to this.

When designing with J-K flip-flops it is advantageous to use both J and K inputs. This will result in simplification of the combinational logic.

When drawing the Karnaugh map for Q0, keep the Q0 and Q0' terms separate.
The same goes for the Q1, Q2 and Q3 flip-flops.

The characteristic equation of the JK flip-flop is:

Thus, the results of the Karnaugh map grouping is applied to the J and K inputs separately.
The result of the combinational logic for the terms for Q' are applied to the J input.
The result of the combinational logic for the terms for Q are inverted and applied to the K input.