Stuck with verilog

Discussion in 'Homework Help' started by aceminer, Oct 15, 2011.

  1. aceminer

    Thread Starter New Member

    Aug 26, 2011
    21
    0
    This is the question.
    Sorry but i do not really get what the question wanted.

    What i have so far is this.

    module Check (input [7:0] a,b,c
    output [7:0] max, min)
    always @*

    begin
    if (a > b> c)
    max = a;
    else if (b>a>c)
    max = b;
    else
    max = c;

    if (a<b<c)
    min = a;
    else if (b<a<c)
    min = b;
    else
    min = c;

    end

    endmodule

    -----------------------------------------------

    Sorry if i seem super newbie as i am just introduced to it recently. Would appreciate any links or URLs to read up on verilog. Thanks in advance.
     
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