Strange CD4013 behaviour?

Discussion in 'General Electronics Chat' started by daviddeakin, Sep 24, 2013.

  1. daviddeakin

    Thread Starter Active Member

    Aug 6, 2009
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    I have the following circuit set up on breadboard. It is supposed to toggle through each of the three outputs each time the button is pressed. At power up, output C should always come on high. As drawn it works as expected.

    BUT! If I eliminate the NOT gate, it does a strange thing. It powers up OK, but the first time the button is pressed it usually goes into a random state (often all outputs high) and locks up. Further presses do nothing.

    I don't understand why this should happen. All that has changed is that the clock changes on the button release rather than the push, and the clock edge may be slower and less clean. But why should the 4013 care if the clock transition is a bit slow? Surely all that should happen is that it might skip through a few states due to extra bouncing, but not lock up?

    Can anyone explain why the NOT gate makes such a huge difference?
     
  2. ronv

    AAC Fanatic!

    Nov 12, 2008
    3,281
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    It has a maximum clock rise time of 10Usec at 10 volts.
     
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  3. daviddeakin

    Thread Starter Active Member

    Aug 6, 2009
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    Well I go to the foot of our stairs. I didn't even know that was a thing!
     
  4. ScottWang

    Moderator

    Aug 23, 2012
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    How are the set pin of 1,2 flip-flop, and the reset pin of 3 flip-flop?
    The clock in of flip-flop of CD4013 is changing the output status by rising edge, when you remove the inverter that it will changed the input clock, and providing a clock from low to hi during the power up.
     
  5. RichardO

    Well-Known Member

    May 4, 2013
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    Your schematic does not show all of the pins of the 4013. You must never leave a CMOS input unconnected. Have you connected all of the Set and Reset pins?
     
  6. daviddeakin

    Thread Starter Active Member

    Aug 6, 2009
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    Sorry, yes the remaining set and reset pins are grounded.
     
  7. Ramussons

    Active Member

    May 3, 2013
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    Is'nt 1 M too high for use as a PullUp/PullDown resistor?

    Ramesh
     
  8. eblc1388

    Senior Member

    Nov 28, 2008
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    In the original circuit, because of initial zero charge in the 100nF inverter input capacitor, the inverter output will be HIGH at power ON and goes to LOW afterwards when the capacitor charges up. This level change on the 4013 clock will not upset or cause any problem to the 4013 F/F.

    By removing the inverter, you are now in effect applying a positive going edge signal to the 4013 clock while they are in the process of being reset. Under this situation, anything can happen as you have found out. Therefore the answer is to hold the clock level steady upon power ON. The following circuit shows you how.

    Another point is even when all three F/Fs output is HIGH, the circuit will still work as usual by passing the nth F/F logic state output to the (n+1)th F/F. However, as the level are now all HIGH, it would seem to you as the circuit has locked up.

    [​IMG]
     
  9. daviddeakin

    Thread Starter Active Member

    Aug 6, 2009
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    But the circuit powers on OK even without the inverter. It only locks up the first time you press the button...
     
  10. eblc1388

    Senior Member

    Nov 28, 2008
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    Your findings led me to build the same circuit and I have encountered the same problem as you have mentioned above.

    Now I can confirm the problem is caused by contact bounce and manifest itself as multiple clockings in the manual push button, or the lack of signal conditioning on the clock edges. These clocking also occurs with improper logic level as seen on an oscilloscope. If I replace the manual clocking by pulse source, the circuit toggles without any problem even at 400 pulses/sec.

    The schmitt trigger inverter in the original circuit takes care of this condition by providing a single clean edge.
     
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