strange 12V Push-Pull inverter waveform

Discussion in 'The Projects Forum' started by JJAngleton, May 15, 2012.

  1. JJAngleton

    JJAngleton Thread Starter New Member

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    Hello to all electronics fans,
    I hope someone has come across a similar situation and can give me some advice.

    I had a truckload of IRFB3207 handy (N-channel MOSFET, 75V, 130 to 180A, 3.6 mohms, Ciss=7600pF) and a large ferrite (EE75) transformer with 2x12V very thick, multi-strand primaries and a 400V secondary tapped at 200V. I Decided to make a DC-DC converter with an SG3525 voltage mode PWM chip at about 40kHz (only without any PWM function, using it as a simple oscillator with complementary, totem-pole driven outputs). The diagram is similar to this Elliot-89 project often mentioned on the internet:

    http://sound.westhost.com/project89.htm

    I am currently at 5xIRFB3207s on each side, directly mounted on two large heatsinks (no isolation, the heatsink aluminum body is used as the conductor between the MOSFET drains and the x-former primaries), and have enough space left on the heatsinks to mount another 2x5 MOSFETS. I am using Japanese 30V/3A/>100MHz transistor pairs (2SB772, 2SD882) as external totem poles to boost the SG3525 output current, instead of the BD139/140 in the Elliot schematic. Bipolar totem-poles are not supposed to suffer shoot-through at pulse crossover, so the emitters are shorted together, no limiting resistors, with the cathode of a 1A 30V schottky(1N5818) connected to the emitters and the anode to ground - allegedly to shunt negative drive pulse ringing. The totem pole emitters drive the paralleled MOSFETS (drains and sources are shorted together) through one gate resistor of 22 ohms and a 15nF polyester capacitor in parallel per MOSFET.

    The secondary is rectified with a bridge made of 12A 1200V fast (FRED) diodes, without filtering capacitors, and various loads have been connected. Up to 600W 220V filament lamps have been tried, tied alternatively to both the 400V and the 200V windings through the rectifier bridge - yeah, I know, 400V is a bit too much for 220V lamps, but they are supposed to take 311V from the 220 AC anyways, and I keep my PWM chip at a low Duty Cycle of 5uS and they seem to sweat it out shining a bit brighter than normal. A universal motor 220V 500W angle grinder has also been tried at the rectified DC of 200 and 400V, works fine at both windings.

    The whole setup is put together without a PC board (save the SG3525 and totem poles), but heavy copper bars are used for ground and transformer connections to avoid stray inductances. For the most part, I would say the load-dependent spikes I get at the switching recoveries are within reason. I am using some simple RC snubbing, but does not seem to have much of an effect.

    I am attaching two scope shots (the scope ground is connected to the negative side of the car battery used to supply the 12V to the inverter, with two 1000uF electrolytics between the +12V primary center tap and the ground):

    In the first picture (DSCN0516-small.jpg), the lower trace shows the MOSFET drain waveform of one side, while the upper trace is the opposite side gate pulse, with a resistive load of 300W lamps at the 200V secondary. We can discern:

    1)a 5uS at 0V when the MOSFETs are on, followed by
    2) 7.5uS of recovery with ringing at some mid voltage close to 12V, and
    3) another 5uS at 2x12V reflected when the other winding is conducting,
    4) dropping back to 12V for another 7.5uS, before the next MOSFET conduction period of 5uS.

    Question 1: the recovery voltage, at pulse interval (2), even after settling down from parasitic ringing, is higher than 12V, (the more so the larger the load), while the dropping back voltage of interval (4) seems correct at 12V. Why is that so ?

    The second picture, (DSCN0517-small.jpg) shows the waveforms at the same points, only with a 500W universal motor angle grinder connected to the 200V secondary winding. One can see that the pulse is totally screwed up.

    Question 2: instead of recovering to 12V after ringing at interval (2), the pulse recovers close to the reflected voltage of 2x12V of interval (3). Interval (4), on the contrary and unexpectedly, goes below 12V. Why is that so ?

    Thanks in advance for your responses.

    Attached Files:

    Last edited: May 15, 2012
  2. JJAngleton

    JJAngleton Thread Starter New Member

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    An additional piece of information: I checked the secondary waveforms, and they are mirroring the primary ones. In other words, this measured primary waveforms are not some kind of spurious pick up, but do reflect MOSFET conduction at times when the MOSFET gates are not biased to conduction. It would appear that the increased oscillations appearing at the gate waveforms upon opposite side MOSFET turn off, are large enough to trigger the MOSFET to some SCR-like latched conduction or semi-conduction state, effectively increasing the duty cycle to 100%. Good thing the MOSFETs do turn off when the totem pole pulls the gate to ground or both sides of the primaries would be conducting simultaneously, with catastrophic results.

    This effect manifests itself only with a universal motor load, even at low output secondary voltages (measuring the secondaries directly, I found out that one end of the secondary gives +-375V, for 750V pp with respect to the center tap, while the other end gives +-100V for 200V pp, so the info I gave earlier for 400V and 200V taps is erroneous). They do not appear with resistive loads, and I am not sure what the waveforms will look like with a simple inductive load (no brushes). I suspect that the gate oscillations are due to the universal motor brushes and not due to some Miller effect thing.

    One solution that comes to mind, is to drive the gate pulse to -5 Volts at turn off. Any oscillations picked up would then hopefully fail to bring the gate to over 0 Volts. Since the noise pick up occurs long after the initial pulse turn off to 0 Volts, it is not clear if a bootstrap construction with a PNP transistor will suffice (for example the "Fixed Base Drive Circuit" in page 177 of the On Semi "Rectifier Applications Handbook" http://www.ieeta.pt/~alex/docs/ApplicationNotes/Rectifier%20Applications%20Handbook.pdf). It may be necessary to make some charge pump or small buck-boost converter circuit to create the -5V for the totem pole.
  3. JJAngleton

    JJAngleton Thread Starter New Member

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    Today's update. Floated the whole SG3525 circuit, including the external totem poles, to -4V from a 18650 lithium battery. I did remove the schottky diodes from the gates, or my battery would get shorted. My pulses are now from about -3.something to +12V. Unfortunately, it does not seem to cut it. I think the noise pick up got worse, I suspect from the long, thin wires from the battery holder to the SG3525 board. With the universal motor connected to the +-375V secondary, I get the following waveforms at DSCN0541-small.jpg (top is MOSFET gate, bottom same side MOSFET drain) , while the ground levels traces for both channels are shown at DSCN0540-small.jpg . The spikes at the gate(s) are very big, especially on the negative side. I must put a bipolar transil or two 15V zeners back to back from the gate to ground to protect the MOSFET gates from overvoltage.

    Next step would be to put the SG3525 circuit in a metal box, and bring the outputs to the gates in a shielded wire. If that fails too, I must make a real bipolar power supply for the SG3525.

    It looks like without a ground plane and appropriate layout it is very difficult to put together a high frequency high current power circuit.

    So far, the only certain conclusion is that the development of such circuits depends entirely on the availability of a CNC PCB setup. Maybe I should put all my efforts into making or purchasing one.

    Attached Files:

  4. gootee

    gootee Active Member

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    Photos of your circuits would probably be extremely helpful.

    You can make proper snubbers fairly easily, since you have a scope. See farther below.

    But you should also try to make sure that you don't have any more antennas than you have to have (both receiving and transmitting), by eliminating as much "enclosed loop area" as possible, by keeping all pairs of conductors as close together as possible, twisting them tightly together whenever you can, for as long as you can. That includes pairs such as AC Mains pair, rectified AC pair, DC power/gnd pairs, signal and gnd pairs, output pair, etc.

    Also, keep low-level conductor pairs away from those carrying high-power and highly-dynamic currents.

    Grounding could also be a problem. Don't share any length of ground conductor between low-level signals and anything else, and especially keep any ground-reference points for signal inputs to active devices all by themselves all the way back to the main ground point.

    Another important thing to think about is decoupling capacitors. Anywhere there is a point of load, where there are sudden demands for current (e.g. a transistor, or a chip), you should have a decoupling capacitor between the power rail and gnd (or whatever the return path is). Otherwise, the inductance of your power rails WILL either make it impossible for the current to be supplied in time, or, a voltage spike will be created on the power rail, or both. The decoupling caps should be as close as possible to the device. Usually, a very small and low-value decoupling cap should also be used in parallel, for high-frequency stability.

    Decoupling cap minimum value can be estimated easily, using an approximation of the differential equation for an ideal capacitor, i = C(dv/dt):

    Rewrite as C = i dt/dv then decide how much voltage disturbance is tolerable on your rail and use that as dv. Use the maximum sudden current change for i and the minimum rise-time of the current change as dt. Remember that C will be in Farads.


    Below is the easy way to get the correct component values for snubbers:

    PRACTICAL SNUBBER AND TERMINATION DESIGN

    Below is a pretty slick and practical way to determine parasitic capacitance and/or inductance, and the characteristic impedance and the optimal damping or termination or snubber resistance (and optional series capacitance) needed when ringing or reflections (as the case may be) are present.This is a very simple method for determining the capacitance and the inductance that are causing a resonance in a circuit or a transmission line or PCB trace, which also gives the characteristic impedance for the resonant circuit, which is everything needed in order to know how to damp it, optimally. (I refer to the C and L as parasitic. But this method and the math may be used when either one, or both, or neither is parasitic, in case an installed inductor and/or capacitor are involved.)

    This assumes that there is a ringing condition, already, such as might occur on a digital buss or a transmission line or PCB trace, or in a switch-mode power supply or even an AC-to-DC transformer/rectifier circuit, and in many other types of circuits. (If you don't have ringing and just want to determine some of these parameters, I guess maybe you could try hitting your circuit with a pulse train and decrease the rise and fall times until it rings.)

    1. Measure the frequency of the resonance or ringing, using an
    oscilloscope (or a circuit simulator, if you've modeled the parasitics well).

    2. Add a shunt capacitor and adjust the value of this capacitor until the frequency of the ringing is reduced by a factor of two. I've left out the math but the value of this resulting capacitor will be three times (3X) the value of the parasitic capacitance that is creating the resonance.

    3. Because the parasitic capacitance is now known, the parasitic inductance can be determined using the formula:

    L = 1 / [(2 · Pi · F)² · C]

    where F = (original) resonant frequency and C = parasitic capacitance.

    4. Now that both the parasitic capacitance and inductance are known, the
    characteristic impedance of the resonant circuit can be determined using the following formula:

    Z = √(L/C)

    where L = parasitic inductance and C = parasitic capacitance.

    5. The resistor value used for the terminator or for the RC snubber circuit should be equal to Z, the value of the characteristic impedance, and the capacitor, if used, should be sized between four and ten times the parasitic capacitance. The use of larger (than 4X) capacitors slightly reduces the voltage overshoot at the expense of greater power dissipation in the resistor.

    NOTE: The resistor, alone, is all that is needed to prevent or damp-out the ringing (or reflections, as the case may be). But if power dissipation in the R would then be too high, a C is added in series with the R, so that only the unwanted frequencies cause currents in the resistor. (And that, boys and girls, is the only reason there's a capacitor in a snubber.)

    Cheers,

    Tom
    Last edited: May 18, 2012
  5. JJAngleton

    JJAngleton Thread Starter New Member

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    Thanks, gootee, for the knowledge dump.
    I am kinda ashamed to post pictures of my prototype, as I could not find any of the rules you set out for antennas and ground loops etc, that I did not violate. I do have decoupling capacitors though at my totem poles driving the MOSFETs - a 10uF electrolytic and a 0.1uF ceramic, but they serve both totem pole pairs (one pair per SG3525 output).

    I am indeed using the heavy copper bar (22 x 3mm) that connects all 10 MOSFET sources to the ground (12V battery negative through a welder type quick connect connector and 2 to 3 feet of heavy gauge wire to a crocodile for the battery connection) as the return path for the drive signals. But I have no choice as the MOSFET sources are connected to the copper bar, and even if I ran a second, thinner wire to their source pins as a return ground connection to the totem poles, I would still be shorting that path to the copper bar with every source pin connection to it,,, the wire would only provide an independent return ground path for the first MOSFET source it would reach in the cascade.

    I have all but given up on this project. I have a small, 600 real Watts capable (though advertized for 1000W) Chinese 12 to 220V DC-AC inverter that I bought cheap from ebay. It is using a pair of DC-DC converters with a single IRF3205 (an improved Chinese version of it, RU6099) per primary push-pull branch and two small EE42 transformers running two push pull stages in parallel, their secondaries each rectified with a discrete diodes bridge, and connected in parallel, feeding a high voltage H bridge for the modified AC formation. The darn little thing has the cleanest square pulses I have ever seen, even under heavy load. No snubbers. Did not try it with the universal motor load though. I should do that. Those poor IRF3205 must carry upwards of 20 Amps each, may be 25A, at 600W, where the current limit kicks in, in a TO220 package. I find that an amazing feat.

    I am mentioning this Chinese little machine because I want to emphasize the apparent reason the manufacturers of such converters are not using a single large transformer and many MOSFETs to get KWatts of performance, but use instead many little ones at the 300W range connected in parallel - this way they avoid the leakage and parasitic pick up problems I am having. I am not sure if the pair I checked has the pulsing interleaved, but it does not really matter, as they are paralleling the DC output of the secondaries. It would also be interesting to see how they implement current limiting when paralleling whole push pull converters. My guess would be at the 220 load, or they would have to provide a current sense component per converter and OR all those signals to a comparator.

    Thanks again for the assistance. If I make any more progress I will post again.
  6. gootee

    gootee Active Member

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    When fully ON, some MOSFETS can have an amazingly-low Rdson (channel "on" resistance), which means that even high currents don't create much i-squared power dissipation. One key, there, is to bang the gates really hard and fast, when turning them on or off, so that they spend as little time as possible in the region BETWEEN on and off, where they DO have (much) higher resistance, which would generate a LOT of heat when there's a lot of current flowing.
  7. JJAngleton

    JJAngleton Thread Starter New Member

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    That concerns the die itself. I have read that one should not push more than 20 or 25A through a TO-220, and the limitation is not the die but the pin to die interconnects. TO-247 can handle much more current, but I am not sure what is the recommended limit on those. IR puts the same die in both packages. It calls the TO-220 part "IRFB" and the TO-247 (or other large one) "IRFP". For example, IRFB3206 has the same die as IRFP3206, but the former is a TO-220 part, the latter a TO-247. Unfortunately, they are both quoted as "wire bond limited" at 120A, while one would be stupid to try pushing the TO-220 to more than 20A. I certainly was (stupid enough) to take the 120A rating on a face value, and I can tell you, they make a nice popping sound when the inside wire bond sublimates to non existence.

    Does anyone know what is the recommended safe amperage one can dump on the TO-247 and other similar thick-legged packages ?
  8. JJAngleton

    JJAngleton Thread Starter New Member

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    In my last question, I meant "for 10 to 20uS, repetitive with DC>=50% ?"
  9. gootee

    gootee Active Member

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    Got it.

    This looks like a fairly-definitive document about all of that:

    http://www.irf.com/technical-info/appnotes/an-1140.pdf

    It looks like both TO-220 and TO-247 IR parts can have either a 15 mil or a 20 mil wire bond size.

    There are a lot of factors to consider, according to that app note. But it does say that the TO-220 with an IRF3205 die with 15 mil wirebonds is conservatively rated for a total (for all three leads) of 75 Amps (25 amps per pin) if there is no attention given to thermal management at the exposed leads (but everything else is done right), and an "ideal" maximum of 120 amps (40 amps per pin) if everything (including lead connections to circuit) is set up as well as possible, thermally (and 160 amps package total when in the lab, immersed in an inert nucleated-boiling liquid). For either of those first two scenarios, from the way they rated it, it looks like you would have to be doing a lot of things correctly in order to get there reliably.
    Last edited: May 19, 2012
  10. JJAngleton

    JJAngleton Thread Starter New Member

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    It looks like my impression about the TO-247 handling more current is not entirely accurate, and I should not give here the wrong impression. Table 1 in the link you gave, states that both the TO-220 and the TO-247 come with varying numbers of 15 mils and 20 mils wires bonding the die to the leg(s). I do not think the data sheets mention that number. Any advantage TO-247 may have over TO-220 is probably entirely due to the larger size of the metal substrate, which must give a better overall dissipation capability. IR mentions a "an overriding limit of 75 Amperes was conservatively set for the overall
    package limit" for TO-220, and after Table 1 repeats "recommended current for all of the packages above is 75A"

    I would still not try anything above 25A with a TO-220. I would probably venture into more than that with a TO-247, just from a gut feeling its heftier size gives me, but no more than 40A in any case.
  11. gootee

    gootee Active Member

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  12. JJAngleton

    JJAngleton Thread Starter New Member

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    Gootee, it is not talking about "all three leads" or "25 Amps per pin". the reference to 3 wires of 15 mils is to the interconnect itself, from each pin of the two that matter (drain and source) to the die. In other words, the lead (pin) comes from the outside world as we see it, into the epoxy encapsulation, terminates somewhere next to, but apart from, the die, and thereafter 3 parallel wires are bonded, with some kind of spot welding process, from the pin to the same area of the die constituting the source or drain. This may be true for the gate as well, but it matters little, as the gate currents can be handled by a single wire.

    Therefore, the total amperages mentioned are per pin (3 wires per pin x 25 amps per wire, gives 75 amps per pin), and not for all 3 pins together (imagine what that would mean, huh ?). You mixed the references to 3 wires with the 3 pins, when it is 3 wires per pin.
  13. gootee

    gootee Active Member

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    DOH!!! Thanks for the clarification!!
  14. The Electrician

    The Electrician Senior Member

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    The problem is due to a point that is often overlooked by beginners designing inverters. If you look at the bottom waveform of your first image, that is what the output waveform of the inverter should look like--a square wave with some dead time.

    The problem arises when your inverter drives an inductive load. During the dead time of your drive waveform, none of the FETs are on. The freewheeling current from the load is clamped to the battery voltage or (a diode drop below) ground by the body diodes in the FETs.

    You must clamp the voltage across the primary of your transformer to zero during the dead time.

    When the inverter topology is an H-bridge, it's possible to turn on both bottom FETs, or both top FETs, at the same time, to provide a short across the transformer primary during the dead time; this causes the inverter output voltage to be zero during the dead time even with an inductive load.

    With a center tapped primary you will have to provide additional FETs to short the primary during the dead time. You could connect a couple of FETs sources together and a drain of one FET to one side of the primary, a drain from the other FET to the other side of the primary, both gates connected together. You will have to provide floating drive to those shorting FETs during the dead time.

    If you don't do this, the inverter output voltage will not be zero during the dead time, as it should be.
  15. JJAngleton

    JJAngleton Thread Starter New Member

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    Thank you very much, Electrician. I did not have time to even look at this forum all this time, but now I will find some time to check your suggestion. Will report if any progress.
  16. JJAngleton

    JJAngleton Thread Starter New Member

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    But, do I care if the inverter primary (or output) voltage is zero during FET dead time ? since this is a reflected to the primary voltage, and only shows up when the load gets no voltage from the secondary, I would assume the proper thing to do would be to somehow provide a freewheeling diode circuit to recycle the inductive load secondary current at the secondary side, as opposed to shorting the primary refelected voltage, because, depending on the inductance of the load, one could have significant reflected currents and therefore dissipate much when shorting the primary. Then again, you say that the shorting happens anyways, except by the drain-to-source inherent MOSFET diodes, so one could not avoid the dissipation anyways, but since they intrinsic diodes do the clamping, and the FETs are thus protected from overvoltage, do I care about providing additional active clamping ? why not let the inverter do its thing with the ugly waveform ?
  17. JJAngleton

    JJAngleton Thread Starter New Member

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    I think I should put a freewheeling diode, with its anode connected to the minus side of the secondary rectifier bridge, and the cathode to the plus - parallel to the load, that is. The coil usually used in such arrangements is probably not necessary, as the load inductance should play that role. This should give a path to any stored energy in the load inductance to recycle itself back to the load during dead time. Comments anyone ?
  18. The Electrician

    The Electrician Senior Member

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    If you're going to be powering an inductive load directly from the secondary and not from the output of the bridge rectifier, then an active short will be necessary if you want the secondary voltage to look like the bottom waveform in your first image.

    But, if you are going to use this as a DC to DC converter (load on the output of the rectifier bridge), then you probably don't need an active short or freewheeling diode.
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