state diagram to state table

Discussion in 'Homework Help' started by icelated, Nov 13, 2010.

  1. icelated

    Thread Starter New Member

    Oct 15, 2010
    12
    0
    I am trying to design a clocked sequential circuit to detect the serial input pattern 1110 The first output will be a 1 after the string 11 is seen. The second output will be 1 only after the entire string has been seen
    Using the state diagram, the state table, the transition table, the excitation table, the k-maps, the equations and the circuit diagram.

    Well i cant draw the circuit diagram. Could someone look at my tables and diagrams and see if they are correct and offer up an idea how to draw this circuit from the k-maps equation using D-flip flops?

    I am trying to get a handle on this! I am just a Software Engineering student that has to take digital logic!
    See attached for diagrams and tables.. Sequence1110.doc

    Thank you
     
    Last edited: Nov 14, 2010
  2. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    Can you post your drawing?

    hgmjr
     
  3. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    Can you scan it?

    hgmjr
     
  4. bertus

    Administrator

    Apr 5, 2008
    15,645
    2,344
    Hello,

    Here is how to attach images from the FAQ:


    Bertus
     
  5. icelated

    Thread Starter New Member

    Oct 15, 2010
    12
    0
    I am trying to design a clocked sequential circuit to detect the serial input pattern 1110 The first output will be a 1 after the string 11 is seen. The second output will be 1 only after the entire string has been seen
    Using the state diagram, the state table, the transition table, the excitation table, the k-maps, the equations and the circuit diagram.

    Well i cant draw the circuit diagram. Could someone look at my tables and diagrams and see if they are correct and offer up an idea how to draw this circuit from the k-maps equation using D-flip flops?

    I am trying to get a handle on this! I am just a Software Engineering student that has to take digital logic!
    See attached for diagrams and tables..

    Thank you
     
  6. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    I have merged your latest thread into this one since it is actually a continuation of the original thread.

    Spawning mulitple thread simply causes confusion on everyone's part.

    hgmjr
     
  7. icelated

    Thread Starter New Member

    Oct 15, 2010
    12
    0
    No one was helping me and i made a totally different file. i wish you would have just deleted my first thread instead of my new one.
     
  8. hgmjr

    Moderator

    Jan 28, 2005
    9,030
    214
    I don't think there will be any problems caused by combining the two posts. Let's give it a little more time. The members are pretty busy and can't always provide answers as rapidly as you may want or need them to. Keep in mind that all of the information here in the forum is provided gratis.

    hgmjr
     
    icelated likes this.
  9. icelated

    Thread Starter New Member

    Oct 15, 2010
    12
    0
    I understand.. Thank you so much! =)
     
  10. Georacer

    Moderator

    Nov 25, 2009
    5,142
    1,266
    Let's begin with the state diagram. This is the core of your circuit and if it isn't correct, all the work will be done in vain.

    As I see it it has some flaws. The general idea is to follow a path while reading the correct input. When something goes wrong (you read something you did'n want to appear) you should send the flow back to the initial state, the one you started the examination of the input at.

    That means that the parts where you stall the examination when you get 0 (I 'm talking about nodes B and C) are incorrect. They should drive the flow to node A and start over.

    Stalling the 1s at D is a good idea, keep it.

    Usually when we recognise the correct sequence we return to the very beginning. That's what the theory of language recognizers say. On successful identification you return to B. This is a mistake because after succesfull identification 110 will cause another succesful identification. Return to A when you read 0 at D.

    Keep in mind that it is invalid to make a transition without any input declared. I 'm talking about the line from A to B.

    Correct your mistakes and post another diagram.
     
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