State diagram of synchronous sequential machine

Discussion in 'Homework Help' started by edgarscat, Oct 14, 2016.

  1. edgarscat

    Thread Starter New Member

    Jul 26, 2016
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    I'm not sure if I'm proceeding well with this exercise:
    Design a synchronous sequential machine with external synchronization which states are coded on 4 bits q_3 q_2 q_1 q_0 whose table is the following:
    <br />
\begin{tabular}{|c|c|c|c|c|c|c|c|}<br />
\hline<br />
q_3 & q_2 & q_1 & q_0 & q_3' & q_2' & q_1' & q_0' \\<br />
\hline<br />
\hline<br />
0 & 0 & 0 & 0 & 0 & 0 & 0 & 1 \\<br />
\hline<br />
0 & 0 & 0 & 1 & 0 & 0 & 1 & 0 \\<br />
\hline<br />
0 & 0 & 1 & 0 & 0 & 1 & 0 & 0 \\<br />
\hline<br />
0 & 0 & 1 & 1 & - & - & - & - \\<br />
\hline<br />
\hline<br />
0 & 1 & 0 & 0 & 0 & 1 & 0 & 1 \\<br />
\hline<br />
0 & 1 & 0 & 1 & 0 & 1 & 1 & 0 \\<br />
\hline<br />
0 & 1 & 1 & 0 & 1 & 0 & 0 & 0 \\<br />
\hline<br />
0 & 1 & 1 & 1 & - & - & - & - \\<br />
\hline<br />
\hline<br />
1 & 0 & 0 & 0 & 1 & 0 & 0 & 1 \\<br />
\hline<br />
1 & 0 & 0 & 1 & 1 & 0 & 1 & 0 \\<br />
\hline<br />
1 & 0 & 1 & 0 & 1 & 1 & 0 & 0 \\<br />
\hline<br />
1 & 0 & 1 & 1 & - & - & - & - \\<br />
\hline<br />
\hline<br />
1 & 1 & 0 & 0 & 1 & 1 & 0 & 1 \\<br />
\hline<br />
1 & 1 & 0 & 1 & 1 & 1 & 1 & 0 \\<br />
\hline<br />
1 & 1 & 1 & 0 & 0 & 0 & 0 & 0 \\<br />
\hline<br />
1 & 1 & 1 & 1 & - & - & - & - \\<br />
\hline<br />
\end{tabular}<br />
    a) Draw the correspondent state diagram.
    b) Design the machine using Flip-Flop D.

    What I'm not sure of is the point "a". Is the diagram I've done correct? Or I missed something?
    State Diagram.png
     
  2. WBahn

    Moderator

    Mar 31, 2012
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    What about the external synchronization it's supposed to have?
     
  3. edgarscat

    Thread Starter New Member

    Jul 26, 2016
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    0
    I'm sorry, I don't get what you mean.
     
  4. WBahn

    Moderator

    Mar 31, 2012
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    Read the problem.

    "Design a synchronous sequential machine with external synchronization which states...."

    You can't solve a problem until you understand what the problem is. Just ignoring a requirement because you don't understand it won't cut it. So if you don't understand what is being asked for, go back to your instructor and ask for clarification. We can guess what is meant -- and probably make pretty good guesses -- but we lack the context to do anything more than guess and engineering isn't about guessing.
     
  5. edgarscat

    Thread Starter New Member

    Jul 26, 2016
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    Isn't the external synchronization about the clock synchronization? With the difference between internal and external synchronization.
     
  6. WBahn

    Moderator

    Mar 31, 2012
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    What is "internal synchronization" referring to?

    That spec is given to you within the context of a text book or a class discussion or something else of which we are not aware. It's meaning depends on that context. You have (or should have) that context. We don't. So if you don't have that context (or don't realize that you do) then you need to get it from whomever gave you the problem, whether that be by reading the text more closely or asking the instructor.

    My best guess is that it is referring to an additional signal that is used to force the machine into a particular state so as synchronize it to other (i.e., external) signals. Think about what would be meant by someone saying that you need to synchronize your watches. The watches themselves keep running both before and after this synchronization event, but before it they were reading times that were not well coordinate whereas after it they are all reading the same thing (as much as possible). But you were only able to synchronize them because there was an additional input that allowed you to override the normal flow of the machine from state to state and force it to go to a particular state of your choice.
     
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  7. edgarscat

    Thread Starter New Member

    Jul 26, 2016
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    The internal synchronization depend on the device, right? Different devices having different clock timing.
    By the way, I understand and I guess I will have to ask the professor about it.
    Thanks for the help anyway!
     
  8. WBahn

    Moderator

    Mar 31, 2012
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    The whole point of a clock is to make the changes happen at, essentially, the same time. The differences between different devices in response to the clock signal should be immaterial to a good design (though never say never).

    I really have no idea what "internal synchronization" would be in this context. I have certainly designed circuits such that different parts of it would automatically become synchronized regardless of how they powered up -- so that could be described as internal synchronization. The key is to ask what it is that is being synchronized -- the very word implies that one thing is being placed in a fixed relationship with something else.

    Aside from the issue of that external synchronization, your state diagram correctly moves between states.
     
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  9. edgarscat

    Thread Starter New Member

    Jul 26, 2016
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    Oh well, I don't think the "internal" one has anything to do with this exercise. I was just saying it to see if we were talking about the same thing.

    Oh okay, I'll ask the professor, although, unfortunately, he will be available on Tuesday... I'll come back here after I get information about this and maybe proceed with the exercise without confusion.
     
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