In a parallel scenario where a driver buffer chip has to drive a long bus, would it make sense to stagger the output of the bits?

Eg. instead of outputing all 8 bits at exactly the same time, do them 1 or 2 bits at a time.

In scenarios where decreasing the slew rate is not possible, would this make sense?

 

What kind of bus? Is there a clock? All bits must arrive at the destination at the same time. If they don't, how you gonna clock them at the input? This is why buses like PCIe were invented.

 

instead of outputing all 8 bits at exactly the same time, do them 1 or 2 bits at a time.

Er .... isn't that serial, not parallel?

 

Brownout:
The bus is asynchronous. You have control over the setup time with your control signals. I should have specified this.

Alec_T:
There are still 8 data lines, just rather than outputting all 8 bits at the same time, I am thinking of outputting them one after the other in close succession, allowing each bit to partially charge its capacitive load before initiating the next.
I think that such a scheme would reduce the current requirements.

 

Brownout:
The bus is asynchronous. You have control over the setup time with your control signals. I should have specified this.

Pardon, but that doesn't make any sense. If it's asynchronous, then there would be no setup time.

 

I think that such a scheme would reduce the current requirements.

It might reduce the peak current requirement, but you are charging the same number of capacitors the same amount, so the total energy will not decrease with staggering.

ak

 

...
There are still 8 data lines, just rather than outputting all 8 bits at the same time, I am thinking of outputting them one after the other in close succession, allowing each bit to partially charge its capacitive load before initiating the next.
I think that such a scheme would reduce the current requirements.

If you are not bothered by increasing the time taken for the signal to stabilise, why not just resistors? That will really reduce the peak current.